`:-, ramfuncs8 .cinit""@.pinit.switch.reset??A.stack.ebss,.econst,,@.esysmemramgs0ramgs1(4?IU`q          @ @ -` ` <ttIttVuucuupH< \\ \\ \\ \\ ]]  ] ] @]@] `]`] . @  R  d\\q\\~ \ \$@@$pp  yyPP  P P @P@P #`P`P 1PP ?PP Mppp[xxpi@@wAABBCCDDEEFFGGHHIIJJKKzz@%QQ"3@Q@Q"AQQ"Ob(t||0zz@ss"@s@s"yy  y y & % 9@R@f@@{``$@`@`$bbH`p`p rrrr r r0r0r^^ ^^aa%aa2 a a?L.[2jy@y@ypp+pppp .ppdataM lp.text.1~P .text.2 .text.3R .text.4 .A,TI%Linker @xV R 4xV  ªêww}ܰҰE̱&xndZPF{I(24 в>*ڲƲ׳ͳóv,"ֱ DN0:h^TJ|r;1'Sqg]!?5+wmc <bXp\HzfR@6Ȱ ۴ѴǴlYO2 C:/C2000F021FlashAPI/cs30_f021_flashapi/SopranoEarlyAPIForEarlyNFL/F021DEV_C2000/API/Source/Fapi/Commands/Info.cC:\C2000F021FlashAPI\cs30_f021_flashapi\SopranoEarlyAPIForEarlyNFL\SopranoEarlyAPIForEarlyNFL_PjtFolder\DebugTI TMS320C2000 Linker PC v15.12.7 Copyright (c) 1996-2017 Texas Instruments Incorporated(Fapi_GlobalInitx_Fapi_GlobalInitAlpha_InternalAlphaBeta_InternalBetaProductionFapi_ApiProductionStatusTyperFapi_FLEPFapi_FLEEFapi_FLESFapi_FLHVFapi_TechTBDFapi_FlashBankTechTypeFapi_Status_SuccessFapi_Status_FsmBusyFapi_Status_FsmReadyFapi_Status_AsyncBusyFapi_Status_AsyncCompleteFapi_Error_FailFapi_Error_StateMachineTimeoutFapi_Error_OtpChecksumMismatchFapi_Error_InvalidDelayValueFapi_Error_InvalidHclkValueFapi_Error_InvalidCpuFapi_Error_InvalidBankFapi_Error_InvalidAddressFapi_Error_InvalidReadModeFapi_Error_AsyncIncorrectDataBufferLengthFapi_Error_AsyncIncorrectEccBufferLengthFapi_Error_AsyncDataEccBufferLengthMismatchFapi_Error_FeatureNotAvailableFapi_StatusType4Fapi_FlashBank0Fapi_FlashBank1Fapi_FlashBank2Fapi_FlashBank3Fapi_FlashBank4Fapi_FlashBank5Fapi_FlashBank6Fapi_FlashBank7Fapi_FlashBankTyper u8ApiMajorVersion#7_u8ApiMajorVersionu8ApiMinorVersion#7_u8ApiMinorVersionu8ApiRevision#7_u8ApiRevisionoApiProductionStatus#_oApiProductionStatusu32ApiBuildNumber#z_u32ApiBuildNumberu8ApiTechnologyType#7_u8ApiTechnologyTypeu8ApiTechnologyRevision#7_u8ApiTechnologyRevisionu8ApiEndianness#7_u8ApiEndiannessu32ApiCompilerVersion# z_u32ApiCompilerVersionFapi_LibraryInfoType u16NumberOfBanks#_u16NumberOfBanksu16Reserved#_u16Reservedu16DeviceMemorySize#_u16DeviceMemorySizeu16DevicePackage#_u16DevicePackageu32AsicId#z_u32AsicIdu32LotNumber#z_u32LotNumberu16WaferNumber#_u16WaferNumberu16FlowCheck# _u16FlowChecku16WaferYCoordinate# _u16WaferYCoordinateu16WaferXCoordinate# _u16WaferXCoordinateFapi_DeviceInfoTypeoFlashBankTech#_oFlashBankTechu32NumberOfSectors#z_u32NumberOfSectorsu32BankStartAddress#z_u32BankStartAddressau8SectorSizes#C_au8SectorSizesFapi_FlashBankSectorsType \ 0ChecksumLength#_ChecksumLengthOtpVersion#_OtpVersionOtpChecksum#z_OtpChecksumNumberOfBanks#_NumberOfBanksNumberOfSectors#_NumberOfSectorsMemorySize#_MemorySizePackage#_PackageSiliconRevision#_SiliconRevisionAsicNumber_23_8#_AsicNumber_23_8AsicNumber_31_24# _AsicNumber_31_24LotNumber# z_LotNumberWaferNumber# _WaferNumberFlowbits# _FlowbitsYCoordinate#_YCoordinateXCoordinate#_XCoordinateEVSU#_EVSUPVSU#_PVSUESU#_ESUPSU#_PSUCVSU #_CVSUAdd_EXEZSU#_Add_EXEZSUPVAcc#_PVAccRVSU#_RVSUPVH2#_PVH2PVH#_PVHRH#_RHPH#_PHSmFrequency #_SmFrequencyVSTAT#_VSTATSequence#_SequenceEH#_EHVHV_EStep#_VHV_EStepVHV_EStart#_VHV_EStartMAX_PP#_MAX_PPOtpReserved1#_OtpReserved1PROG_PW#_PROG_PWMAX_EP#_MAX_EPERA_PW#z_ERA_PWVHV_E# _VHV_EVHV_P#!_VHV_PVINH#"_VINHVCG#"_VCGVHV_PV##_VHV_PVOtpReserved2#$_OtpReserved2VRead#$_VReadVWL_P#%_VWL_PVSL_P#%_VSL_PApiChecksum#&z_ApiChecksumOtpReserved3#(z_OtpReserved3OtpReserved4#*z_OtpReserved4OtpReserved5#,z_OtpReserved5OtpReserved6#.z_OtpReserved6+ )RM#_RM_FRDCNTL_Reserved_03_01 #__FRDCNTL_Reserved_03_01ASWSTEN #_ASWSTEN_FRDCNTL_Reserved_07_05#__FRDCNTL_Reserved_07_05RWAIT#_RWAIT_FRDCNTL_Reserved_15_12#__FRDCNTL_Reserved_15_12IDLEN#_IDLEN_FRDCNTL_Reserved_23_17#__FRDCNTL_Reserved_23_17IFLUSH_HOLD#_IFLUSH_HOLD_FRDCNTL_Reserved_31_28#__FRDCNTL_Reserved_31_28RM0#_RM0RM1#_RM1_FSPRD_Reserved_07_02#__FSPRD_Reserved_07_02RMBSEM#_RMBSEMDIS_PREEMPT#_DIS_PREEMPT_FSPRD_Reserved_31_17#__FSPRD_Reserved_31_17EDACEN #_EDACENEZCV #_EZCVEOCV #_EOCV_FEDACCTRL1_Reserved_07_06#__FEDACCTRL1_Reserved_07_06EPEN#_EPENEZFEN#_EZFENEOFEN#_EOFEN_FEDACCTRL1_Reserved_15_11#__FEDACCTRL1_Reserved_15_11EDACMODE #_EDACMODE_FEDACCTRL1_Reserved_23_20#__FEDACCTRL1_Reserved_23_20SUSP_IGNR#_SUSP_IGNR_FEDACCTRL1_Reserved_31_25#__FEDACCTRL1_Reserved_31_25SEC_THRESHOLD#_SEC_THRESHOLD_FEDACCTRL2_Reserved_31_16#__FEDACCTRL2_Reserved_31_16COR_ERR_CNT#_COR_ERR_CNT_FCOR_ERR_CNT_Reserved_31_16#__FCOR_ERR_CNT_Reserved_31_16SERR_POS#_SERR_POSECC_ERR#_ECC_ERRB2_ERR#_B2_ERR_FCOR_ERR_POS_Reserved_15_10#__FCOR_ERR_POS_Reserved_15_10_FCOR_ERR_POS_Reserved_31_16#__FCOR_ERR_POS_Reserved_31_16ERR_PRF_FLG#_ERR_PRF_FLGERR_ZERO_FLG#_ERR_ZERO_FLGERR_ONE_FLG #_ERR_ONE_FLGD_COR_ERR #_D_COR_ERRECC0_MAL_ERR #_ECC0_MAL_ERRECC1_MAL_ERR #_ECC1_MAL_ERRCOM0_MAL_GOOD #_COM0_MAL_GOODCOM1_MAL_GOOD#_COM1_MAL_GOODECC_MUL_ERR#_ECC_MUL_ERRBUF_PAR_ERR#_BUF_PAR_ERRADD_PAR_ERR#_ADD_PAR_ERRADD_TAG_ERR#_ADD_TAG_ERRD_UNC_ERR#_D_UNC_ERRB2_ERR_IS_EE#_B2_ERR_IS_EE_FEDACSTATUS_Reserved_15_14#__FEDACSTATUS_Reserved_15_14B2_COR_ERR#_B2_COR_ERRB2_UNC_ERR#_B2_UNC_ERRECCB2_MAL_ERR #_ECCB2_MAL_ERRCOMB2_BUS_MAL_GOOD #_COMB2_BUS_MAL_GOODECC2_MAL_ERR #_ECC2_MAL_ERRECC3_MAL_ERR #_ECC3_MAL_ERRCOM2_MAL_GOOD #_COM2_MAL_GOODCOM3_MAL_GOOD#_COM3_MAL_GOODFSM_DONE#_FSM_DONERVF_INT#_RVF_INT_FEDACSTATUS_Reserved_31_26#__FEDACSTATUS_Reserved_31_26SectorID0 #_SectorID0_FEDACSDIS_Reserved_04 #__FEDACSDIS_Reserved_04BankID0#_BankID0SectorID0_inverse#_SectorID0_inverse_FEDACSDIS_Reserved_12#__FEDACSDIS_Reserved_12BankID0_inverse#_BankID0_inverseSectorID1 #_SectorID1_FEDACSDIS_Reserved_20 #__FEDACSDIS_Reserved_20BankID1#_BankID1SectorID1_inverse#_SectorID1_inverse_FEDACSDIS_Reserved_28#__FEDACSDIS_Reserved_28BankID1_inverse#_BankID1_inversePRIM_ADD_TAG_0_15#_PRIM_ADD_TAG_0_15PRIM_ADD_TAG_16_22 #_PRIM_ADD_TAG_16_22_FPRIM_ADD_TAG_Reserved_31_23 #__FPRIM_ADD_TAG_Reserved_31_23REDU_ADD_TAG_0_15#_REDU_ADD_TAG_0_15REDU_ADD_TAG_16_22 #_REDU_ADD_TAG_16_22_FREDU_ADD_TAG_Reserved_31_23 #__FREDU_ADD_TAG_Reserved_31_23PROTL1DIS#_PROTL1DIS_FBPROT_Reserved_15_02#__FBPROT_Reserved_15_02_FBPROT_Reserved_31_16#__FBPROT_Reserved_31_16BSE#_BSE_FBSE_Reserved_31_16#__FBSE_Reserved_31_16BUSY#_BUSY_FBBUSY_Reserved_15_08#__FBBUSY_Reserved_15_08_FBBUSY_Reserved_31_06#__FBBUSY_Reserved_31_06VREADS#_VREADSBAGP#_BAGPOTPPROTDIS#_OTPPROTDIS_FBAC_Reserved_31_24#__FBAC_Reserved_31_24BANKPWR0#_BANKPWR0BANKPWR1 #_BANKPWR1BANKPWR2 #_BANKPWR2BANKPWR3#_BANKPWR3BANKPWR4#_BANKPWR4BANKPWR5#_BANKPWR5BANKPWR6#_BANKPWR6BANKPWR7#_BANKPWR7REG_PWRSAV #_REG_PWRSAV_FBAC_Reserved_23_20#__FBAC_Reserved_23_20FSM_PWRSAV#_FSM_PWRSAV_FBAC_Reserved_31_28#__FBAC_Reserved_31_28BANKRDY#_BANKRDY_FBPRDY_Reserved_14_08#__FBPRDY_Reserved_14_08PUMPRDY#_PUMPRDYBANKBUSY#_BANKBUSY_FBPRDY_Reserved_31_24#__FBPRDY_Reserved_31_24PUMPPWR#_PUMPPWR_FBAC1_Reserved_15_01#__FBAC1_Reserved_15_01PSLEEPTDIS #_PSLEEPTDIS_FBAC1_Reserved_31_27#__FBAC1_Reserved_31_27PAGP#_PAGP_FBAC2_Reserved_31_16#__FBAC2_Reserved_31_16BANK #_BANK_FMAC_Reserved_15_03 #__FMAC_Reserved_15_03_FMAC_Reserved_31_15#__FMAC_Reserved_31_15SLOCK#_SLOCKPSUSP#_PSUSPESUSP #_ESUSPVOLSTAT #_VOLSTATCSTAT #_CSTATINVDAT #_INVDATPGM #_PGMERS#_ERSBusy#_BusyCV#_CVEV#_EVPCV#_PCVPGV#_PGVDBF#_DBFILA#_ILARVF#_RVFRDVER#_RDVERRVSUSP#_RVSUSP_FMSTAT_Reserved_31_18#__FMSTAT_Reserved_31_18EMU_ECC#_EMU_ECC_FEMU_ECC_Reserved_15_08#__FEMU_ECC_Reserved_15_08_FEMU_ECC_Reserved_31_16#__FEMU_ECC_Reserved_31_16ENCOM#_ENCOM_FLOCK_Reserved_31_16#__FLOCK_Reserved_31_16EMU_ADDR_15_0#_EMU_ADDR_15_0EMU_ADDR_21_16 #_EMU_ADDR_21_16_FEMU_ADDR_Reserved_31_22 #__FEMU_ADDR_Reserved_31_22DIAGMODE #_DIAGMODE_FDIAGCTRL_Reserved_07_03#__FDIAGCTRL_Reserved_07_03DIAG_BUF_SEL#_DIAG_BUF_SEL_FDIAGCTRL_Reserved_11_10#__FDIAGCTRL_Reserved_11_10DIAG_ECC_SEL#_DIAG_ECC_SEL_FDIAGCTRL_Reserved_15#__FDIAGCTRL_Reserved_15DIAG_EN_KEY #_DIAG_EN_KEY_FDIAGCTRL_Reserved_23_20#__FDIAGCTRL_Reserved_23_20DIAG_TRIG#_DIAG_TRIG_FDIAGCTRL_Reserved_31_25#__FDIAGCTRL_Reserved_31_25RAW_ECC#_RAW_ECC_FRAW_ECC_Reserved_15_08#__FRAW_ECC_Reserved_15_08_FRAW_ECC_Reserved_31_16#__FRAW_ECC_Reserved_31_16DAT_INV_PAR#_DAT_INV_PARADD_INV_PAR#_ADD_INV_PARPAR_OVR_KEY#_PAR_OVR_KEYBUS_PAR_DIS#_BUS_PAR_DISBNK_INV_PAR#_BNK_INV_PAR_FPAR_OVR_Reserved_31_17#__FPAR_OVR_Reserved_31_17VREADCT #_VREADCT_FVREADCT_Reserved_15_04 #__FVREADCT_Reserved_15_04_FVREADCT_Reserved_31_16#__FVREADCT_Reserved_31_16VHVCT_PV #_VHVCT_PV_FVHVCT1_Reserved_15_09#__FVHVCT1_Reserved_15_09VHVCT_E #_VHVCT_E_FVHVCT1_Reserved_31_25#__FVHVCT1_Reserved_31_25VHVCT_C #_VHVCT_C_FVHVCT2_Reserved_15_09#__FVHVCT2_Reserved_15_09VHVCT_P #_VHVCT_P_FVHVCT2_Reserved_31_25#__FVHVCT2_Reserved_31_25VHVCT_READ #_VHVCT_READ_FVHVCT3_Reserved_15_09#__FVHVCT3_Reserved_15_09WCT #_WCT_FVHVCT3_Reserved_31_20 #__FVHVCT3_Reserved_31_20VIN_CT #_VIN_CT_FVNVCT_Reserved_07_05#__FVNVCT_Reserved_07_05VCG2P5CT#_VCG2P5CT_FVNVCT_Reserved_15_13#__FVNVCT_Reserved_15_13_FVNVCT_Reserved_31_16#__FVNVCT_Reserved_31_16_FVLSP_Reserved_11_00 #__FVLSP_Reserved_11_00VSL_P#_VSL_P_FVLSP_Reserved_31_16#__FVLSP_Reserved_31_16VWLCT_P #_VWLCT_P_FVWLCT_Reserved_15_05 #__FVWLCT_Reserved_15_05_FVWLCT_Reserved_31_16#__FVWLCT_Reserved_31_16EFUSE_EN #_EFUSE_ENEF_TEST #_EF_TEST_FEFUSECTRL_Reserved_07_05#__FEFUSECTRL_Reserved_07_05EF_CLRZ#_EF_CLRZ_FEFUSECTRL_Reserved_15_09#__FEFUSECTRL_Reserved_15_09BP_SEL#_BP_SELWRITE_EN#_WRITE_EN_FEFUSECTRL_Reserved_23_18#__FEFUSECTRL_Reserved_23_18CHAIN_SEL#_CHAIN_SEL_FEFUSECTRL_Reserved_31_27#__FEFUSECTRL_Reserved_31_27SHIFT_DONE#_SHIFT_DONE_FEFUSE_Reserved_15_01#__FEFUSE_Reserved_15_01_FEFUSE_Reserved_31_16#__FEFUSE_Reserved_31_16SEQ_PUMP#_SEQ_PUMP_FSEQPMP_Reserved_15_08#__FSEQPMP_Reserved_15_08_FSEQPMP_Reserved_31_15#__FSEQPMP_Reserved_31_15CLK_TRIM_0_15#_CLK_TRIM_0_15CLK_TRIM_18_16 #_CLK_TRIM_18_16_FCLKTRIM_Reserved_31_19 #__FCLKTRIM_Reserved_31_19SectorID2 #_SectorID2_FEDACSDIS2_Reserved_4 #__FEDACSDIS2_Reserved_4BankID2#_BankID2SectorID2_inverse#_SectorID2_inverse_FEDACSDIS2_Reserved_12#__FEDACSDIS2_Reserved_12BankID2_inverse#_BankID2_inverseSectorID3 #_SectorID3_FEDACSDIS2_Reserved_20 #__FEDACSDIS2_Reserved_20BankID3#_BankID3SectorID3_inverse#_SectorID3_inverse_FEDACSDIS2_Reserved_28#__FEDACSDIS2_Reserved_28BankID3_inverse#_BankID3_inverse_FBSTROBES_Reserved_01_00#__FBSTROBES_Reserved_01_00TEZ #_TEZOTP #_OTPTI_OTP #_TI_OTPPRECOL #_PRECOLNOCOLRED #_NOCOLRED_FBSTROBES_Reserved_07#__FBSTROBES_Reserved_07CTRLENZ#_CTRLENZ_FBSTROBES_Reserved_15_9#__FBSTROBES_Reserved_15_9FCLKEN#_FCLKEN_FBSTROBES_Reserved_23_17#__FBSTROBES_Reserved_23_17ECBIT#_ECBIT_FBSTROBES_Reserved_31_25#__FBSTROBES_Reserved_31_25_5VPWRDNZ#__5VPWRDNZ_3VPWRDNZ#__3VPWRDNZ_FBSTROBES_Reserved_07_02#__FBSTROBES_Reserved_07_02EXECUTEZ#_EXECUTEZ_FPSTROBES_Reserved_15_09#__FPSTROBES_Reserved_15_09_FPSTROBES_Reserved_31_16#__FPSTROBES_Reserved_31_16MODE #_MODE_FBMODE_Reserved_15_03 #__FBMODE_Reserved_15_03_FBMODE_Reserved_31_16#__FBMODE_Reserved_31_16TCR #_TCR_FTCR_Reserved_15_07 #__FTCR_Reserved_15_07_FTCR_Reserved_31_16#__FTCR_Reserved_31_16ADDR_INCR #_ADDR_INCRTP_BUSY_SEL#_TP_BUSY_SELFL_DATAIN_SEL#_FL_DATAIN_SELTP_DATA_SEL#_TP_DATA_SELWDAT_CHANGE #_WDAT_CHANGESW_MODE #_SW_MODE_FPMT_CTRL_Reserved_31_21 #__FPMT_CTRL_Reserved_31_21PBIST_KEY #_PBIST_KEYGRP1_EN #_GRP1_EN_PBIST_CTRL_Reserved_15_05 #__PBIST_CTRL_Reserved_15_05_PBIST_CTRL_Reserved_31_16#__PBIST_CTRL_Reserved_31_16_FTCTRL_Reserved_00#__FTCTRL_Reserved_00TEST_EN#_TEST_EN_FTCTRL_Reserved_15_02#__FTCTRL_Reserved_15_02WDATA_BLK_CLR#_WDATA_BLK_CLR_FTCTRL_Reserved_23_17#__FTCTRL_Reserved_23_17AUTOCALC_EN#_AUTOCALC_EN_FTCTRL_Reserved_31_25#__FTCTRL_Reserved_31_25WPDATA_287_256#z_WPDATA_287_256u8Bytes31_24#_u8Bytes31_24u8Bytes23_16#_u8Bytes23_16u8Bytes15_08#_u8Bytes15_08u8Bytes07_00#_u8Bytes07_00SAFELV#_SAFELV_FSWSTAT_Reserved_15_01#__FSWSTAT_Reserved_15_01_FSWSTAT_Reserved_31_16#__FSWSTAT_Reserved_31_16CLKSEL#_CLKSEL_FSM_GLBCTRL_Reserved_15_01#__FSM_GLBCTRL_Reserved_15_01_FSM_GLBCTRL_Reserved_31_16#__FSM_GLBCTRL_Reserved_31_16_FSM_STATE_Reserved_05_00 #__FSM_STATE_Reserved_05_00OTP_ACT #_OTP_ACTTIOTP_ACT#_TIOTP_ACTFSM_ACT#_FSM_ACT_FSM_STATE_Reserved_09#__FSM_STATE_Reserved_09EXECUTEZ#_EXECUTEZCTRLENZ#_CTRLENZ_FSM_STATE_Reserved_15_12#__FSM_STATE_Reserved_15_12_FSM_STATE_Reserved_31_16#__FSM_STATE_Reserved_31_16INV_DAT#_INV_DATOVR_PUL_CNT#_OVR_PUL_CNTNON_OP #_NON_OP_FSM_STATUS_Reserved_15_03 #__FSM_STATUS_Reserved_15_03_FSM_STATUS_Reserved_31_16#__FSM_STATUS_Reserved_31_16FSMCMD #_FSMCMD_FSM_COMMAND_Reserved_15_06 #__FSM_COMMAND_Reserved_15_06_FSM_COMMAND_Reserved_31_16#__FSM_COMMAND_Reserved_31_16ERA_OSU#_ERA_OSUPGM_OSU#_PGM_OSU_FSM_PE_OSU_Reserved_31_16#__FSM_PE_OSU_Reserved_31_16_FSM_VSTAT_Reserved_11_00 #__FSM_VSTAT_Reserved_11_00VSTAT_CNT#_VSTAT_CNT_FSM_VSTAT_Reserved_31_16#__FSM_VSTAT_Reserved_31_16ERA_VSU#_ERA_VSUPGM_VSU#_PGM_VSU_FSM_PE_VSU_Reserved_31_16#__FSM_PE_VSU_Reserved_31_16CMP_VSU #_CMP_VSUADD_EXZ#_ADD_EXZ_FSM_CMP_VSU_Reserved_31_16#__FSM_CMP_VSU_Reserved_31_16EXE_VALD#_EXE_VALDREP_VSU#_REP_VSU_FSM_EX_VAL_Reserved_31_16#__FSM_EX_VAL_Reserved_31_16RD_H#_RD_H_FSM_RD_H_Reserved_15_08#__FSM_RD_H_Reserved_15_08_FSM_RD_H_Reserved_31_16#__FSM_RD_H_Reserved_31_16_FSM_P_OH_Reserved_07_00#__FSM_P_OH_Reserved_07_00PGM_OH#_PGM_OH_FSM_P_OH_Reserved_31_16#__FSM_P_OH_Reserved_31_16ERA_OH#_ERA_OH_FSM_ERA_OH_Reserved_31_16#__FSM_ERA_OH_Reserved_31_16SAV_P_PUL #_SAV_P_PUL_FSM_SAV_PPUL_Reserved_15_12#__FSM_SAV_PPUL_Reserved_15_12_FSM_SAV_PPUL_Reserved_31_16#__FSM_SAV_PPUL_Reserved_31_16ERA_VH#_ERA_VHPGM_VH#_PGM_VH_FSM_PE_VH_Reserved_31_16#__FSM_PE_VH_Reserved_31_16PROG_PUL_WIDTH#_PROG_PUL_WIDTH_FSM_PRG_PW_Reserved_31_16#__FSM_PRG_PW_Reserved_31_16SAV_ERA_PUL #_SAV_ERA_PUL_FSM_SAV_ERA_PUL_Reserved_15_12#__FSM_SAV_ERA_PUL_Reserved_15_12_FSM_SAV_ERA_PUL_Reserved_31_16#__FSM_SAV_ERA_PUL_Reserved_31_16CMD #_CMDMODE #_MODESAV_ERA_MODE#_SAV_ERA_MODESAV_PGM_CMD#_SAV_PGM_CMDSUBMODE#_SUBMODEERA_SUBMODE#_ERA_SUBMODEPGM_SUBMODE#_PGM_SUBMODERDV_SUBMODE #_RDV_SUBMODE_FSM_MODE_Reserved_31_20 #__FSM_MODE_Reserved_31_20PGM_ADDR_15_0#_PGM_ADDR_15_0PGM_ADDR_22_16 #_PGM_ADDR_22_16PGM_BANK#_PGM_BANK_FSM_PGM_Reserved_27_26#__FSM_PGM_Reserved_27_26SAV_SEC#_SAV_SECERA_ADDR_15_0#_ERA_ADDR_15_0ERA_ADDR_22_16 #_ERA_ADDR_22_16ERA_BANK#_ERA_BANK_FSM_ERA_Reserved_31_26#__FSM_ERA_Reserved_31_26MAX_PRG_PUL #_MAX_PRG_PUL_FSM_PRG_PUL_Reserved_15_12#__FSM_PRG_PUL_Reserved_15_12BEG_EC_LEVEL #_BEG_EC_LEVEL_FSM_PRG_PUL_Reserved_31_25#__FSM_PRG_PUL_Reserved_31_25MAX_ERA_PUL #_MAX_ERA_PUL_FSM_ERA_PUL_Reserved_15_12#__FSM_ERA_PUL_Reserved_15_12MAX_EC_LEVEL #_MAX_EC_LEVEL_FSM_ERA_PUL_Reserved_31_25#__FSM_ERA_PUL_Reserved_31_25_FSM_STEP_SIZE_Reserved_15_00#__FSM_STEP_SIZE_Reserved_15_00EC_STEP_SIZE #_EC_STEP_SIZE_FSM_STEP_SIZE_Reserved_31_25#__FSM_STEP_SIZE_Reserved_31_25PUL_CNTR #_PUL_CNTR_FSM_PUL_CNTR_Reserved_15_12#__FSM_PUL_CNTR_Reserved_15_12CUR_EC_LEVEL #_CUR_EC_LEVEL_FSM_PUL_CNTR_Reserved_31_25#__FSM_PUL_CNTR_Reserved_31_25EC_STEP_HEIGHT #_EC_STEP_HEIGHT_FSM_EC_STEP_HEIGHT_Reserved_15_7 #__FSM_EC_STEP_HEIGHT_Reserved_15_7_FSM_EC_STEP_HEIGHT_Reserved_31_16#__FSM_EC_STEP_HEIGHT_Reserved_31_16OVERRIDE#_OVERRIDEINV_DATA#_INV_DATACMD_EN #_CMD_ENDIS_TST_EN #_DIS_TST_ENPREC_STOP_EN #_PREC_STOP_ENPGM_SEC_COF_EN #_PGM_SEC_COF_ENBNK_ERA_MODE #_BNK_ERA_MODEDBG_SHORT_ROW#_DBG_SHORT_ROWDO_REDU_COL#_DO_REDU_COL_FSM_ST_MACHINE_Reserved_12#__FSM_ST_MACHINE_Reserved_12RESTRT_ADDR#_RESTRT_ADDRONE_TIME_GOOD#_ONE_TIME_GOOD_FSM_ST_MACHINE_Reserved_15#__FSM_ST_MACHINE_Reserved_15RV_INT_EN#_RV_INT_ENRV_RES#_RV_RESRV_SEC_EN #_RV_SEC_ENRANDOM #_RANDOMCMPV_ALLOWED #_CMPV_ALLOWEDALL_BANKS #_ALL_BANKSFSM_INT_EN #_FSM_INT_ENDO_PRECOND#_DO_PRECOND_FSM_ST_MACHINE_Reserved_31_24#__FSM_ST_MACHINE_Reserved_31_24WR_ENA #_WR_ENA_FSM_WR_ENA_Reserved_15_03 #__FSM_WR_ENA_Reserved_15_03_FSM_WR_ENA_Reserved_31_16#__FSM_WR_ENA_Reserved_31_16ACC_EP#_ACC_EP_FSM_ACC_EP_Reserved_31_16#__FSM_ACC_EP_Reserved_31_16SEC_OUT #_SEC_OUTSECTOR#_SECTOR_FSM_SECTOR_Reserved_15_08#__FSM_SECTOR_Reserved_15_08SECT_ERASED#_SECT_ERASEDCONFIG_CRC #_CONFIG_CRCMOD_VERSION_15_12#_MOD_VERSION_15_12MOD_VERSION_31_16#_MOD_VERSION_31_16FSMEXECUTE #_FSMEXECUTE_FSM_EXECUTE_Reserved_15_05 #__FSM_EXECUTE_Reserved_15_05SUSPEND_NOW #_SUSPEND_NOW_FSM_EXECUTE_Reserved_31_20 #__FSM_EXECUTE_Reserved_31_20AUTOSTART_GRACE#_AUTOSTART_GRACEAUTOSUSP_EN#_AUTOSUSP_EN_EEPROM_CONFIG_Reserved_15_09#__EEPROM_CONFIG_Reserved_15_09EWAIT #_EWAIT_EEPROM_CONFIG_Reserved_31_20 #__EEPROM_CONFIG_Reserved_31_20MAIN_NUM_BANK #_MAIN_NUM_BANKMAIN_BANK_WIDTH #_MAIN_BANK_WIDTHEE_NUM_BANK #_EE_NUM_BANKEE_BANK_WIDTH #_EE_BANK_WIDTHCPU_TYPE1 #_CPU_TYPE1UERR #_UERRAUTO_SUSP#_AUTO_SUSPECCA#_ECCASIL3#_SIL3IFLUSH#_IFLUSHROM#_ROMEE_IN_MAIN#_EE_IN_MAINCPU2_FCFG #_CPU2_FCFGMEM_MAP #_MEM_MAPAUTOCALC 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#_B0_SECT_SIZE_FCFG_B0_SSIZE0_Reserved_15_4 #__FCFG_B0_SSIZE0_Reserved_15_4B0_NUM_SECTORS #_B0_NUM_SECTORS_FCFG_B0_SSIZE0_Reserved_31_28#__FCFG_B0_SSIZE0_Reserved_31_28B0_SECT_SIZE_4#_B0_SECT_SIZE_4B0_SECT_SIZE_5#_B0_SECT_SIZE_5B0_SECT_SIZE_6#_B0_SECT_SIZE_6B0_SECT_SIZE_7#_B0_SECT_SIZE_7_FCFG_B0_SSIZE1_Reserved_31_0#z__FCFG_B0_SSIZE1_Reserved_31_0B0_SECT_SIZE_8#_B0_SECT_SIZE_8B0_SECT_SIZE_9#_B0_SECT_SIZE_9B0_SECT_SIZE_10#_B0_SECT_SIZE_10B0_SECT_SIZE_11#_B0_SECT_SIZE_11_FCFG_B0_SSIZE2_Reserved_31_0#z__FCFG_B0_SSIZE2_Reserved_31_0B0_SECT_SIZE_12#_B0_SECT_SIZE_12B0_SECT_SIZE_13#_B0_SECT_SIZE_13B0_SECT_SIZE_14#_B0_SECT_SIZE_14B0_SECT_SIZE_15#_B0_SECT_SIZE_15_FCFG_B0_SSIZE3_Reserved_31_0#z__FCFG_B0_SSIZE3_Reserved_31_0B1_SECT_SIZE_0#_B1_SECT_SIZE_0B1_SECT_SIZE_1#_B1_SECT_SIZE_1B1_SECT_SIZE_2#_B1_SECT_SIZE_2B1_SECT_SIZE_3#_B1_SECT_SIZE_3B1_SECT_SIZE #_B1_SECT_SIZE_FCFG_B1_SSIZE0_Reserved_15_4 #__FCFG_B1_SSIZE0_Reserved_15_4B1_NUM_SECTORS #_B1_NUM_SECTORS_FCFG_B1_SSIZE0_Reserved_31_28#__FCFG_B1_SSIZE0_Reserved_31_28B1_SECT_SIZE_4#_B1_SECT_SIZE_4B1_SECT_SIZE_5#_B1_SECT_SIZE_5B1_SECT_SIZE_6#_B1_SECT_SIZE_6B1_SECT_SIZE_7#_B1_SECT_SIZE_7_FCFG_B1_SSIZE1_Reserved_31_0#z__FCFG_B1_SSIZE1_Reserved_31_0B1_SECT_SIZE_8#_B1_SECT_SIZE_8B1_SECT_SIZE_9#_B1_SECT_SIZE_9B1_SECT_SIZE_10#_B1_SECT_SIZE_10B1_SECT_SIZE_11#_B1_SECT_SIZE_11_FCFG_B1_SSIZE2_Reserved_31_0#z__FCFG_B1_SSIZE2_Reserved_31_0B1_SECT_SIZE_12#_B1_SECT_SIZE_12B1_SECT_SIZE_13#_B1_SECT_SIZE_13B1_SECT_SIZE_14#_B1_SECT_SIZE_14B1_SECT_SIZE_15#_B1_SECT_SIZE_15_FCFG_B1_SSIZE3_Reserved_31_0#z__FCFG_B1_SSIZE3_Reserved_31_0B2_SECT_SIZE_0#_B2_SECT_SIZE_0B2_SECT_SIZE_1#_B2_SECT_SIZE_1B2_SECT_SIZE_2#_B2_SECT_SIZE_2B2_SECT_SIZE_3#_B2_SECT_SIZE_3B2_SECT_SIZE #_B2_SECT_SIZE_FCFG_B2_SSIZE0_Reserved_15_4 #__FCFG_B2_SSIZE0_Reserved_15_4B2_NUM_SECTORS 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#_B3_NUM_SECTORS_FCFG_B3_SSIZE0_Reserved_31_28#__FCFG_B3_SSIZE0_Reserved_31_28B3_SECT_SIZE_4#_B3_SECT_SIZE_4B3_SECT_SIZE_5#_B3_SECT_SIZE_5B3_SECT_SIZE_6#_B3_SECT_SIZE_6B3_SECT_SIZE_7#_B3_SECT_SIZE_7_FCFG_B3_SSIZE1_Reserved_31_0#z__FCFG_B3_SSIZE1_Reserved_31_0B3_SECT_SIZE_8#_B3_SECT_SIZE_8B3_SECT_SIZE_9#_B3_SECT_SIZE_9B3_SECT_SIZE_10#_B3_SECT_SIZE_10B3_SECT_SIZE_11#_B3_SECT_SIZE_11_FCFG_B3_SSIZE2_Reserved_31_0#z__FCFG_B3_SSIZE2_Reserved_31_0B3_SECT_SIZE_12#_B3_SECT_SIZE_12B3_SECT_SIZE_13#_B3_SECT_SIZE_13B3_SECT_SIZE_14#_B3_SECT_SIZE_14B3_SECT_SIZE_15#_B3_SECT_SIZE_15_FCFG_B3_SSIZE3_Reserved_31_0#z__FCFG_B3_SSIZE3_Reserved_31_0B4_SECT_SIZE_0#_B4_SECT_SIZE_0B4_SECT_SIZE_1#_B4_SECT_SIZE_1B4_SECT_SIZE_2#_B4_SECT_SIZE_2B4_SECT_SIZE_3#_B4_SECT_SIZE_3B4_SECT_SIZE #_B4_SECT_SIZE_FCFG_B4_SSIZE0_Reserved_15_4 #__FCFG_B4_SSIZE0_Reserved_15_4B4_NUM_SECTORS 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#_B7_NUM_SECTORS_FCFG_B7_SSIZE0_Reserved_31_28#__FCFG_B7_SSIZE0_Reserved_31_28B7_SECT_SIZE_4#_B7_SECT_SIZE_4B7_SECT_SIZE_5#_B7_SECT_SIZE_5B7_SECT_SIZE_6#_B7_SECT_SIZE_6B7_SECT_SIZE_7#_B7_SECT_SIZE_7_FCFG_B7_SSIZE1_Reserved_31_0#z__FCFG_B7_SSIZE1_Reserved_31_0B7_SECT_SIZE_8#_B7_SECT_SIZE_8B7_SECT_SIZE_9#_B7_SECT_SIZE_9B7_SECT_SIZE_10#_B7_SECT_SIZE_10B7_SECT_SIZE_11#_B7_SECT_SIZE_11_FCFG_B7_SSIZE2_Reserved_31_0#z__FCFG_B7_SSIZE2_Reserved_31_0B7_SECT_SIZE_12#_B7_SECT_SIZE_12B7_SECT_SIZE_13#_B7_SECT_SIZE_13B7_SECT_SIZE_14#_B7_SECT_SIZE_14B7_SECT_SIZE_15#_B7_SECT_SIZE_15_FCFG_B7_SSIZE3_Reserved_31_0#z__FCFG_B7_SSIZE3_Reserved_31_0 m_poTiOtpBaseAddress#^_m_poTiOtpBaseAddressm_poFlashControlRegisters# _m_poFlashControlRegistersm_u8MainBankWidth#7_m_u8MainBankWidthm_u8EeBankWidth#7_m_u8EeBankWidthm_u8MainEccWidth#7_m_u8MainEccWidthm_u8EeEccWidth#7_m_u8EeEccWidthm_u8CurrentRwait#7_m_u8CurrentRwaitm_u8CurrentEwait# 7_m_u8CurrentEwaitm_u16HclkFrequency# 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#_Bx_NUM_SECTORS_FCFG_Bx_SSIZE0_Reserved_31_28#__FCFG_Bx_SSIZE0_Reserved_31_28Bx_SECT_SIZE_4#_Bx_SECT_SIZE_4Bx_SECT_SIZE_5#_Bx_SECT_SIZE_5Bx_SECT_SIZE_6#_Bx_SECT_SIZE_6Bx_SECT_SIZE_7#_Bx_SECT_SIZE_7_FCFG_Bx_SSIZE1_Reserved_31_0#z__FCFG_Bx_SSIZE1_Reserved_31_0Bx_SECT_SIZE_8#_Bx_SECT_SIZE_8Bx_SECT_SIZE_9#_Bx_SECT_SIZE_9Bx_SECT_SIZE_10#_Bx_SECT_SIZE_10Bx_SECT_SIZE_11#_Bx_SECT_SIZE_11_FCFG_Bx_SSIZE2_Reserved_31_0#z__FCFG_Bx_SSIZE2_Reserved_31_0Bx_SECT_SIZE_12#_Bx_SECT_SIZE_12Bx_SECT_SIZE_13#_Bx_SECT_SIZE_13Bx_SECT_SIZE_14#_Bx_SECT_SIZE_14Bx_SECT_SIZE_15#_Bx_SECT_SIZE_15_FCFG_Bx_SSIZE3_Reserved_31_0#z__FCFG_Bx_SSIZE3_Reserved_31_0`OTP_VALUE#_OTP_VALUEau8OtpWord#W_au8OtpWordau16OtpWord#-_au16OtpWordau32OtpWord#_au32OtpWordFapi_TiOtpBytesType D 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P _all  _bit 8 .eos fH 1  ` _ACQPS _rsvd1 _CHSEL_rsvd2_TRIGSEL_rsvd3.eosfP B  h _all  _bit P .eos f` R  _SOC0_SOC1_SOC2_SOC3_SOC4_SOC5_SOC6_SOC7_SOC8_SOC9 _SOC10 _SOC11 _SOC12 _SOC13 _SOC14_SOC15.eosfh c  _all _bit h .eos f s  _SOC0_SOC1_SOC2_SOC3_SOC4_SOC5_SOC6_SOC7_SOC8_SOC9 _SOC10 _SOC11 _SOC12 _SOC13 _SOC14_SOC15.eosf   _all _bit  .eos f   _SOC0_SOC1_SOC2_SOC3_SOC4_SOC5_SOC6_SOC7_SOC8_SOC9 _SOC10 _SOC11 _SOC12 _SOC13 _SOC14_SOC15.eosf   _all _bit  .eos f   _SOC0_SOC1_SOC2_SOC3_SOC4_SOC5_SOC6_SOC7_SOC8_SOC9 _SOC10 _SOC11 _SOC12 _SOC13 _SOC14_SOC15.eosf   _all _bit  .eos f  " _rsvd1 .eosf  * _all _bit  .eos f"   _ADCCTL1 _ADCCTL2 # \00 |;@ fIP T` bp p ~ "                 @  `      %  1 0 = H I  ` U@  b` ( o @ | X  p    P_rsvd1  _rsvd20@ $_rsvd3P` _rsvd4p>  l_ADCREV  0_rsvd5>@ B r  R0&@  5`  D S a p      B  "0@ T ` h  z  "1  @  _rsvd6>O \  i@ v`   _rsvd7>@.eosf*    0@P`p&3@MZgt b    @ 2 `  .eosf   _rsvd1>  C   C _rsvd2@> _TSNSCTL` k_rsvd3p>p_LOCK F _rsvd4>``   4  J  ` _rsvd5> .eosf    $/< _rsvd1_rsvd2.eosf F  & _all  _bit  .eos f W  4 $/< _rsvd1_rsvd2.eosf& i  < _all  _bit & .eos f4 z  J $/< _rsvd1_rsvd2.eosf<   R _all  _bit < .eos fJ   ` $/< _rsvd1_rsvd2.eosfR   h _all  _bit R .eos f`  r _CSFA_CSFB_rsvd1 .eosfh  z _all _bit h .eos fr   _T1U_T1D_T2U_T2D_rsvd1.eosfz   _all _bit z .eos f   _ZRO_PRD_CAU_CAD_CBU_CBD _rsvd1 .eosf   _all _bit  .eos f   _T1U_T1D_T2U_T2D_rsvd1.eosf   _all _bit  .eos f *  _ZRO_PRD_CAU_CAD_CBU_CBD _rsvd1 .eosf 7  _all _bit  .eos f C  OZe_rsvd1r_rsvd2 _rsvd3 .eosf   _all _bit  .eos f   _ACTSFA_OTSFA_ACTSFB_OTSFB_RLDCSF_rsvd1.eosf   _all _bit  .eos f   _T1SEL_T2SEL_rsvd1.eosf  " _all _bit  .eos f   : _ASIZE_TA_R_HOLD_R_SETUP _W_HOLD_W_SETUP_EW_SS.eosf"   B _all  _bit " .eos f:    Z _ASIZE_TA_R_HOLD_R_SETUP _W_HOLD_W_SETUP_EW_SS.eosfB $  b _all  _bit B .eos fZ 6   z _ASIZE_TA_R_HOLD_R_SETUP _W_HOLD_W_SETUP_EW_SS.eosfb I  _all  _bit b .eos fz [   l _rsvd1_rsvd2_rsvd3_rsvd4_rsvd5_rsvd6_WP0_rsvd7_rsvd8_rsvd9.eosf z  _all  _bit  .eos f   _rsvd1_rsvd2.eosf  _all  _bit  .eos f   _PLLEN _rsvd1_rsvd2.eosf  _all  _bit  .eos f   _IMULT_rsvd1_FMULT_rsvd2 _rsvd3.eosf  _all  _bit  .eos f !  _LOCKS_SLIPS_rsvd1_rsvd2.eosf !  _all  _bit  .eos f %!  7!_rsvd1 .eosf C! _all _bit  .eos f T!  _rsvd1 .eosfe! _all _bit .eos f u!  !_rsvd1_rsvd2.eosf !  &_all  _bit  .eos f !  0_CEINTEN_rsvd1_rsvd2.eosf& !  8_all  _bit & .eos f0 !  B!_rsvd1_rsvd2.eosf8 !  J_all  _bit 8 .eos fB !  T!_rsvd1_rsvd2.eosfJ !  \_all  _bit J .eos fT "  l""("_rsvd1_rsvd2 _rsvd3.eosf\ 3"  t_all  _bit \ .eos fl @"  ""("_rsvd1_rsvd2 _rsvd3.eosft N"  _all  _bit t .eos f ["  ""("_rsvd1_rsvd2 _rsvd3.eosf i"  _all  _bit  .eos f v"  _MODE_rsvd1"_DEMUXA_rsvd2 _DRA_rsvd3_rsvd4.eosf "  _all  _bit  .eos f "  _BCNT_LCNT.eosf "  _all  _bit  .eos f "  _LOFFSET_rsvd1.eosf "  _all  _bit  .eos f "  _BCNT_LCNT.eosf "  _all  _bit  .eos f "  _ACT_PEND_rsvd1_WM_rsvd2_rsvd3.eosf "  _all  _bit  .eos f #  _BCNT_LCNT.eosf #  _all  _bit  .eos f #  _LOFFSET_rsvd1.eosf /#  (_all  _bit  .eos f  =#  0_BCNT_LCNT.eosf( J#  8_all  _bit ( .eos f0 V#  H_ACT_PEND_rsvd1_WM_rsvd2_rsvd3.eosf8 c#  P_all  _bit 8 .eos fH _CH_REGS _MODE I_CONTROL o#  {#0  #@#P#`#p#### $$*$:$I$ ^$  o$@ $` $ $ $ $ .eosfP$  _TASK1_TASK2_TASK3_TASK4.eosf $  _all  _bit  .eos f %  _TASK5_TASK6_TASK7_TASK8.eosf "%  _all  _bit  .eos f 7%  P%a%_rsvd1_rsvd2.eosf r%  _all  _bit  .eos f % _MVECT1_MVECT2_MVECT3 _MVECT40_MVECT5@_MVECT6P_MVECT7`_MVECT8p_rsvd1>_MCTL H_rsvd2>_MIFR $I_MIOVF BI_MIFRC  I_MICLR0 H%@ H_MIERP H_MIRUN` `I_rsvd3p__MPC_rsvd4__MAR0__MAR1__MSTF r __MR0 _rsvd5> __MR1  _rsvd6@> __MR2` _rsvd7> __MR3 .eosf% @ % 8b % Xb .eosf@%  0%%%% &&!&-&_rsvd1_rsvd2 9& E& S& a& _rsvd3_LOSPCP_rsvd4.eosf  o&  8_all  _bit   .eos f0 &  B_SEM_rsvd1_KEY.eosf8 &  J_all  _bit 8 .eos fB &  \&_rsvd1&_XTALOFF_WDHALTI_rsvd2 _rsvd3.eosfJ &  d_all  _bit J .eos f\ &  v&&'_rsvd1_rsvd2_rsvd3 _rsvd4.eosfd '  ~_all  _bit d .eos fv '  1'_rsvd1 _rsvd2.eosf~ ='  _all  _bit ~ .eos f M'  _CLKSEM B [' 0 _rsvd1@>@% \ % v %  % e _rsvd2>@!&@ e h'` e -&  _rsvd3>@9&  s'  E&  le S&@  a&` S ~' Bp _rsvd4> _LOSPCP "F _MCDCR G _X1CNT tn .eosf '  _CMPAHR_CMPA.eosf '  _all  _bit  .eos f '  _CMPBHR_CMPB.eosf '  _all  _bit  .eos f ' '''_rsvd1'_rsvd2' ' _rsvd3.eosf( _all _bit .eos f( !(,(7(_rsvd1B(_rsvd2M(X( c( n( _rsvd3.eosfy(  _all _bit .eos f( \_COMPCTL x( _COMPSTS (0 (@ _rsvd1P(` (p (_rsvd2(_rsvd3(_rsvd4(_rsvd5_RAMPSTS_rsvd6(  )0 )@ [)P [%)` |3)p fD) VR) @c) _rsvd7>P.eosf m) x{)))))_rsvd1)) ) ) )).eosf\) _all _bit \.eos fx* *"*_SELREF.*;*_rsvd1F*.eosfP* _all _bit .eos f`* _COMPHYS_rsvd1 .eosfq* _all _bit .eos f* _COMPCTL(_DACCTL_CTRIP_rsvd1_rsvd2 .eosf* _all _bit .eos f* _rsvd1**_rsvd2* * _rsvd3 .eosf* _all _bit .eos f* *+_rsvd1++ _rsvd2 .eosf'+ _all _bit .eos f4+ _RUN_HALTB+M+X+_SYNCFRC_SYNCCLR_ERRCLRc+_SYNCFLG _SYNCERR n+ {+ _RUNSTS _OVRFLG_rsvd1.eosf+  _all _bit .eos f+  *_RESET_rsvd1_KEY.eosf  +  2_all  _bit   .eos f* +  X_EPWM1_EPWM2_EPWM3_EPWM4_EPWM5_EPWM6_EPWM7_EPWM8_EPWM9_EPWM10 _EPWM11 _EPWM12 _rsvd1 _rsvd2 _rsvd3_rsvd4_rsvd5.eosf2 +  `_all  _bit 2 .eos fX +  p_ADC_A_ADC_B_ADC_C_ADC_D_rsvd1 _rsvd2.eosf` +  x_all  _bit ` .eos fp +  _CMPSS1_CMPSS2_CMPSS3_CMPSS4_CMPSS5_CMPSS6_CMPSS7_CMPSS8_rsvd1_rsvd2.eosfx +  _all  _bit x .eos f ,  _rsvd1_rsvd2_rsvd3_rsvd4_rsvd5 _DAC_A_DAC_B_DAC_C_rsvd6_rsvd7 .eosf ,  _all  _bit  .eos f %,  _ECAP1_ECAP2_ECAP3_ECAP4_ECAP5_ECAP6_rsvd1_rsvd2_rsvd3_rsvd4.eosf 3,  _all  _bit  .eos f @,  _EQEP1_EQEP2_EQEP3_rsvd1_rsvd2 _rsvd3.eosf N,  _all  _bit  .eos f [,  _rsvd1_rsvd2_rsvd3_rsvd4_rsvd5_rsvd6_rsvd7_rsvd8_rsvd9_rsvd10.eosf i,  _all  _bit  .eos f v,  (_SD1_SD2_rsvd1_rsvd2_rsvd3_rsvd4_rsvd5_rsvd6_rsvd7_rsvd8.eosf ,  0_all  _bit  .eos f( ,  @_SCI_A_SCI_B_SCI_C_SCI_D_rsvd1 _rsvd2.eosf0 ,  H_all  _bit 0 .eos f@ ,  \_SPI_A_SPI_B_SPI_C_rsvd1_rsvd2 _rsvd3_rsvd4_rsvd5.eosfH ,  d_all  _bit H .eos f\ ,  t_I2C_A_I2C_B_rsvd1_rsvd2_rsvd3_rsvd4.eosfd ,  |_all  _bit d .eos ft ,  _CAN_A_CAN_B_rsvd1_rsvd2_rsvd3 _rsvd4.eosf| ,  _all  _bit | .eos f ,  _McBSP_A_McBSP_B_rsvd1_rsvd2.eosf -  _all  _bit  .eos f -  *-7-F-_PCLKCR0_PCLKCR1_PCLKCR2_PCLKCR3_PCLKCR4_PCLKCR5_PCLKCR6 _PCLKCR7 _PCLKCR8 _PCLKCR9 S- ]-g-q-{---_SECMSEL_LPMCR--_rsvd1.eosf -  _all  _bit  .eos f - _TIM Pf _PRD TZ _TCR@ $f_rsvd1P_TPR` f_TPRHp tf.eosf-  8-  _rsvd1 >@*-` 7- 4D F- HX _rsvd2>`_PCLKCR0  Q _PCLKCR1@ R _PCLKCR2` R _PCLKCR3 R _PCLKCR4 R _rsvd3> _PCLKCR6 S _PCLKCR7 4S _PCLKCR8  PS _PCLKCR9@ hS S-` Q ]- R g- *R q- BR {- bR _rsvd4> -  R _rsvd5@>0_SECMSEL@ a _LPMCR`  - df _rsvd6> _RESC ~\ .eosf - @. _rsvd1 .eosf8. H_all _bit 8.eos f@2. V_rsvd1_SAMPWIN_THRESH _rsvd2_FILINIT.eosfHE. ^_all _bit H.eos fVW. f. _rsvd1 .eosf^m. n_all _bit ^.eos ff. |_rsvd1_SAMPWIN_THRESH _rsvd2_FILINIT.eosfn. _all _bit n.eos f|. ._rsvd1._rsvd2_SYNCSEL_rsvd3.eosf. _all _bit .eos f. _DACVAL _rsvd1 .eosf. _all _bit .eos f. _DACVAL _rsvd1 .eosf/ _all _bit .eos f/ _DACCTL_DACVAL/_rsvd1 .eosf'/ _all _bit .eos f4/ _DACVAL _rsvd1 .eosfC/ _all _bit .eos fQ/ _DACVAL _rsvd1 .eosf`/ _all _bit .eos fn/ /_rsvd1.eosf}/ _all _bit .eos f/ _REV_rsvd1.eosf/ _all _bit .eos f/ /_rsvd1_rsvd2 .eosf/ "_all _bit .eos f/ *_DACVALA _rsvd1 .eosf"/ 2_all _bit ".eos f*/ :_DACVALS _rsvd1 .eosf2/ B_all _bit 2.eos f:0 V_DACREV _DACCTL _DACVALA *_DACVALS0 :/@ _DACLOCKP _DACTRIM` _rsvd1p.eosfB 0 `0(0_rsvd1 .eosfV70 h_all _bit V.eos f`C0 O0_POLSEL_IN_MODEY0f0s0 0 _OUTSWAP 00.eosfh0 _all _bit h.eos f0 _rsvd1_rsvd2_rsvd3_DBFEDHR .eosf0 _all _bit .eos f0 _rsvd1_rsvd2_rsvd3_DBREDHR .eosf0 _all _bit .eos f0  0_rsvd1_rsvd2.eosf _DC0_REG  _all  _bit  .eos f 0  _I2C_A_I2C_B_rsvd1_rsvd2_rsvd3_rsvd4.eosf 1  _all  _bit  .eos f 1  _CAN_A_CAN_B_rsvd1_rsvd2_rsvd3 _rsvd4.eosf 1  _all  _bit  .eos f )1  _McBSP_A_McBSP_B_rsvd1_USB_A_rsvd2_rsvd3 .eosf 41  _all  _bit  .eos f >1  _uPP_A_rsvd1_rsvd2_rsvd3.eosf  I1  _all  _bit   .eos f S1  ._ADC_A_ADC_B_ADC_C_ADC_D_rsvd1 _rsvd2.eosf ^1  6_all  _bit  .eos f. h1  N_CMPSS1_CMPSS2_CMPSS3_CMPSS4_CMPSS5_CMPSS6_CMPSS7_CMPSS8_rsvd1_rsvd2.eosf6 s1  V_all  _bit 6 .eos fN }1  n_rsvd1_rsvd2_rsvd3_rsvd4_rsvd5 _DAC_A_DAC_B_DAC_C_rsvd6_rsvd7 .eosfV 1  v_all  _bit V .eos fn 1  _LS0_1_LS1_1_LS2_1_LS3_1_LS4_1_LS5_1_rsvd1 _rsvd2.eosfv 1  _all  _bit v .eos f 1  _LS0_2_LS1_2_LS2_2_LS3_2_LS4_2_LS5_2_rsvd1 _rsvd2.eosf 1  _all  _bit  .eos f 1  1111_rsvd11_rsvd22_rsvd3 _rsvd4 _rsvd5.eosf _DC1_REG  _all  _bit  .eos f 2  _GS0_GS1_GS2_GS3_GS4_GS5_GS6_GS7_GS8_GS9 _GS10 _GS11 _GS12 _GS13 _GS14_GS15_rsvd1.eosf 2  _all  _bit  .eos f !2  _EMIF1_EMIF2_rsvd1_rsvd2.eosf _DC2_REG  _all  _bit  .eos f  +2  8_EPWM1_EPWM2_EPWM3_EPWM4_EPWM5_EPWM6_EPWM7_EPWM8_EPWM9_EPWM10 _EPWM11 _EPWM12 _rsvd1 _rsvd2 _rsvd3_rsvd4_rsvd5.eosf _DC3_REG  @_all  _bit  .eos f8 52  X_ECAP1_ECAP2_ECAP3_ECAP4_ECAP5_ECAP6_rsvd1_rsvd2_rsvd3_rsvd4.eosf@ _DC4_REG  `_all  _bit @ .eos fX ?2  p_EQEP1_EQEP2_EQEP3_rsvd1_rsvd2 _rsvd3.eosf` _DC5_REG  x_all  _bit ` .eos fp I2  _rsvd1_rsvd2_rsvd3_rsvd4_rsvd5_rsvd6_rsvd7_rsvd8_rsvd9_rsvd10.eosfx _DC6_REG  _all  _bit x .eos f S2  _SD1_SD2_rsvd1_rsvd2_rsvd3_rsvd4_rsvd5_rsvd6_rsvd7_rsvd8.eosf _DC7_REG  _all  _bit  .eos f ]2  _SCI_A_SCI_B_SCI_C_SCI_D_rsvd1 _rsvd2.eosf _DC8_REG  _all  _bit  .eos f g2  _SPI_A_SPI_B_SPI_C_rsvd1_rsvd2 _rsvd3_rsvd4_rsvd5.eosf _DC9_REG  _all  _bit  .eos f q2 ~2222_rsvd122 _rsvd2 .eosf2 _all _bit .eos f2 ,223 33%313=3I3U3 b3 o3 _rsvd1 |3 3_rsvd2.eosf3 4_all _bit .eos f,3 X223 33%313=3I3U3 b3 o3 _rsvd1 |3 3_rsvd2.eosf43 `_all _bit 4.eos fX3 t~2222_rsvd122 _rsvd2 .eosf`3 |_all _bit `.eos ft3 223 33%313=3I3U3 b3 o3 _rsvd1 |3 3_rsvd2.eosf|3 _all _bit |.eos f4 223 33%313=3I3U3 b3 o3 _rsvd1 |3 3_rsvd2.eosf4 _all _bit .eos f)4 _CAPE84_rsvd1 _rsvd2 _rsvd3_rsvd4.eosfB4 _all _bit .eos fP4 _SRCSEL_BLANKE]4g4_rsvd1_rsvd2_rsvd3_rsvd4 _rsvd5 .eosfq4  _all _bit .eos f}4 _FLSEM ! 4 b _RAMSTAT@ [ _rsvd1`> .eosf 4 04 _rsvd1 > 4@ _rsvd2`> 4 _rsvd3>`4 _rsvd4 > 4@ _rsvd5`>5 .eosf5 @T5 q /5 q >5@ p K5` _rsvd1>^5 j5  v5@ 5` _rsvd2_Z1_CR q5 q 5 q 5 fq 5 8q _rsvd3 .eosf0@5 n5 _rsvd1 > 5@ _rsvd2`> 5 _rsvd3>`6 _rsvd4 > #6@ _rsvd5`>26 .eosfTB6 @P6 r `6 r o6@ q |6` _rsvd1>6 6  6@ 6` _rsvd2_Z2_CR  r6 r 6 zr 6 Xr 6 *r _rsvd3 .eosfn@6  77%727 .eosf?7 _all _bit .eos fN7 _rsvd1_FREE.eosf^7 _all _bit .eos fm7  _CPUSEL0_CPUSEL1_CPUSEL2_CPUSEL3_CPUSEL4_CPUSEL5_CPUSEL6_CPUSEL7_CPUSEL8_CPUSEL9 7 7 7 7 7_rsvd1_rsvd2.eosf 7  _all  _bit  .eos f 7 t7  _rsvd1 >`_PARTIDL Q _PARTIDH Q _REVID _rsvd2> _DC0  _DC1   _DC2@   _DC3` 8 _DC4 X _DC5 p _DC6  _DC7  _DC8  _DC9   _DC10@  _DC11`  _DC12  _DC13  _DC14 . _DC15 N _rsvd3> _DC17  n _DC18@  _DC19`  _DC20  _rsvd4>`&_PERCNF1 S _rsvd5 > _FUSEERR@ p" _rsvd6`> 7  pb 7@ b 7` "c 7 Bc 8 Zc 8 zc 8 c *8 c 58 c @8@ c _rsvd7` > K8 b _rsvd8 > W8 b c8 b _rsvd9 > o8 b _rsvd10@ > 2_CPUSEL0` X _CPUSEL1  _CPUSEL2  _CPUSEL3  _CPUSEL4 ( _CPUSEL5 @ _CPUSEL6  \ _CPUSEL7@ t _CPUSEL8`  _CPUSEL9  _rsvd11> 7 p 7  _rsvd12> 7   _rsvd13@>.{8  * _RSTSTAT@ \_LPMSTATP LF_rsvd14`>.eosf8  _DLYDIS_DLYCTL_rsvd1 _rsvd2.eosft 8  _all  _bit t .eos f 8  _CH1_CH2_CH3_CH4.eosf 8  _all  _bit  .eos f 8  _CH5_CH6_rsvd1.eosf 8  _all  _bit  .eos f 8  99_rsvd1_rsvd2.eosf 9  _all  _bit  .eos f 19 ?9J9_rsvd1.eosfY9 _all _bit .eos ff9 |9  _rsvd1 > 9@  P%`  a%  _rsvd2> 9`  9  .eosf9 _DMACTRL 9 _rsvd0 _rsvd109@ dZ_rsvd2P9` xZ_rsvd3p>_CH1P_CH2P_CH3P_CH4P_CH5 P_CH6 P.eosf9 _LWLB_LWHB.eosf9 _all _bit .eos f9  _HWLB_HWHB.eosf9 (_all _bit .eos f 9 0_LWLB_LWHB.eosf(: 8_all _bit (.eos f0: @_HWLB_HWHB.eosf8: H_all _bit 8.eos f@':  Z_rsvd18:F:_rsvd2T:b:_rsvd3.eosfH p:  b_all  _bit H .eos fZ :  p_rsvd1::_rsvd2 _rsvd3.eosfb :  x_all  _bit b .eos fp :  ::::_rsvd1 _rsvd2.eosfx :  _all  _bit x .eos f ;  _INIT_M0_INIT_M1_INIT_D0_INIT_D1_rsvd1 _rsvd2.eosf ;  _all  _bit  .eos f !;  _rsvd1_LOCK_D0_LOCK_D1_rsvd2 _rsvd3.eosf .;  _all  _bit  .eos f :;  _TEST_M0_TEST_M1_TEST_D0_TEST_D1_rsvd1_rsvd2.eosf G;  _all  _bit  .eos f S; _TSCTR _CTRPHS  _CAP1@ _CAP2` _CAP3 _CAP4 _rsvd1>_ECCTL1@ ._ECCTL2P N_ECEINT` ~_ECFLGp _ECCLR  _ECFRC _rsvd2>`.eosf^;  _INT_CEVT1_CEVT2_CEVT3_CEVT4_CTROVF_CTR_PRD_CTR_CMP_rsvd1.eosfj; _all _bit .eos f u; ._CAP1POL_CTRRST1_CAP2POL_CTRRST2_CAP3POL_CTRRST3_CAP4POL_CTRRST4_CAPLDEN ;.eosf; 6_all _bit .eos f.; N;;_REARM;;;_SWSYNC; _APWMPOL _rsvd1 .eosf6; V_all _bit 6.eos fN;  `_ENABLE_rsvd1 _rsvd2.eosfV <  h_all  _bit V .eos f` < ~_rsvd1_CEVT1_CEVT2_CEVT3_CEVT4_CTROVF"<.<_rsvd2.eosfh:< _all _bit h.eos f~F< _INT_CEVT1_CEVT2_CEVT3_CEVT4_CTROVF_CTR_PRD_CTR_CMP_rsvd1.eosfR< _all _bit .eos f]< _rsvd1_CEVT1_CEVT2_CEVT3_CEVT4_CTROVF_CTR_PRD_CTR_CMP_rsvd2.eosfi< _all _bit .eos ft<  <<<_rsvd1 _rsvd2.eosf <  _all  _bit  .eos f <  <_rsvd1_rsvd2.eosf <  _all  _bit  .eos f <  =_rsvd1_rsvd2.eosf =  _all  _bit  .eos f *=  :=_rsvd1_KEY.eosf F=  _all  _bit  .eos f U= h=  s=  =@  _rsvd1`> =  _rsvd2>`.eosf=  *<<_rsvd1_rsvd2.eosf =  2_all  _bit  .eos f* =  <=_rsvd1_rsvd2.eosf2 =  D_all  _bit 2 .eos f< =  N>_rsvd1_rsvd2.eosfD >  V_all  _bit D .eos fN > d0> N ;> < _rsvd1@>@H> * _rsvd2>`.eosfVW> _RCSR X\ b>  n>@ ha x>` |a > : > Z > z _rsvd1> > a _rsvd2 >`> > _rsvd3> > a _INT_RAW $D _INT_MSK  C >@ D >` C _rsvd4>H.eosfd?  _DPEI_UOEI_rsvd1_EOWI_EOLI_rsvd2_DPEQ_UOEQ _rsvd3 _EOWQ _EOLQ _rsvd4 _rsvd5.eosf ?  _all  _bit  .eos f ?  ,?7?A?K? U?_rsvd1_?.eosf l?  _all  _bit  .eos f {? _TBCTL e_TBCTL2 e_rsvd1 > _TBCTR@_TBSTSP f_rsvd2`> _CMPCTL _CMPCTL2 _rsvd3> _DBCTL _DBCTL2 `_rsvd4> _AQCTL  ?  _rsvd5 > _PCCTL@ Q_rsvd6P> _HRCNFG JA_HRPWR A_rsvd7 >@_HRMSTEP` ZA_rsvd8p>`_HRPCTL rA_rsvd9>`_GLDCTL@ "_GLDCFGP "_rsvd10`> ?  _rsvd11>`_AQCTLA  _AQCTLA2  _AQCTLB   _AQCTLB20  _rsvd12@>0_AQSFRCp  _rsvd13_AQCSFRC r _rsvd14>`_DBREDHR _DBRED_DBFEDHR  _DBFED0_rsvd15@> _TBPHS e _TBPRDHR _TBPRD0_rsvd16@>`_CMPA  _CMPB  _rsvd17_CMPC_rsvd18_CMPD_rsvd19 > _GLDCTL2@ "_rsvd20P> _TZSEL zm_rsvd21_TZDCSEL  l_rsvd220_TZCTL@ l_TZCTL2P bl?` xl?p l_rsvd23>P_TZEINT l_rsvd24>P_TZFLG0 l?@ ,l?P Nm_rsvd25` _TZCLRp Jl? l? 0m_rsvd26 _TZFRC m_rsvd27 >_ETSEL@ | _rsvd28P _ETPS` \ _rsvd29p _ETFLG  _rsvd30 _ETCLR _rsvd31 _ETFRC , _rsvd32 _ETINTPS > _rsvd33 _ETSOCPS  _rsvd34 ? _rsvd350 ?@  _rsvd36P > ? _rsvd37 > _DCACTL0 _DCBCTL@ t_rsvd38P > _DCFCTLp ? @ @ @ *@ _rsvd39 > _DCCAP _rsvd40 > 8@ ,E@0 XR@@ _@P _rsvd41` >*.eosfl@ |@ h @ h @@ Ji @` vi @ i @ j @ j @ j A 6k "A  bk 5A@ f HA` f \A ^g oA g A h A .h A i A  i A@ fj A`  k A k A 2g B g B zh _rsvd1>-B k _rsvd2>@9B k .eosfCB  (_QPOSCNT NB  _QPOSMAX@ _QPOSCMP` XB bB _QPOSLAT _QUTMR _QUPRD _QWDTMR _QWDPRD0_QDECCTL@ Z_QEPCTLP .[_QCAPCTL` Z_QPOSCTLp [_QEINT  [_QFLG r[_QCLR Z_QFRC [_QEPSTS L[_QCTMR_QCPRDlBvB_rsvd1.eosf B  0_ERR_CNT_rsvd1.eosf( B  8_all  _bit ( .eos f0 B  DBB_rsvd1_rsvd2.eosf8 B  L_all  _bit 8 .eos fD B  XBC_rsvd1_rsvd2.eosfL C  `_all  _bit L .eos fX #C  t1C_rsvd1 _INTPRD2_INTCNT2_rsvd1.eosf4 tE F _all _bit 4 .eos f> E \ _INTPRD_INTCNTEE_rsvd1_SOCAPRD_SOCACNT _SOCBPRD _SOCBCNT.eosfF E d _all _bit F .eos f\ E | _INTSEL_INTENEEE_rsvd1_SOCASEL_SOCAEN _SOCBSEL _SOCBEN.eosfd E  _all _bit d .eos f| E  EEFF .eosf F  _all _bit  .eos f 'F  =FIFUFaFmFyFFFFF F F _rsvd1 FFFFG GG$G0G_FBAC  H ! _FBPRDY  ! _FPAC1@ " _FPAC2`  " _FMAC ! _FMSTAT ! _rsvd2>@TH H" .eosfd! H !H ` H  H@ I` I +I  _ERR_POS t 7I  _ERR_CNT 0 ^D   GI@ X SI` D _I lI yI  I \! I 2! I  I@ I` J! .eosf!I  !_SEM_rsvd1_KEY_rsvd2.eosf! I  !_all  _bit ! .eos f! I  !_BANK_rsvd1 _rsvd2.eosf! I  !_all  _bit ! .eos f! I  !_rsvd1_rsvd2_rsvd3I_CSTAT_INVDAT_PGM_ERS_BUSY_rsvd4 _EV _rsvd5 _PGV _rsvd6 _ILA_rsvd7_rsvd8_rsvd9_rsvd10.eosf! J  "_all  _bit ! .eos f! J  "_PMPPWR_rsvd1_PSLEEP _rsvd2.eosf" J  "_all  _bit " .eos f" &J  "_PAGP_rsvd1.eosf" 2J  ("_all  _bit " .eos f " =J  4"_rsvd1_RWAIT_rsvd2 _rsvd3.eosf(" KJ  <"_all  _bit (" .eos f4" XJ  H"lJyJ_rsvd1_rsvd2.eosf<" J  P"_all  _bit <" .eos fH" J  \"_RM0_RM1_rsvd1_rsvd2.eosfP" J  d"_all  _bit P" .eos f\" J  p"_ALERR_ERR_rsvd1 _rsvd2.eosfd" J  x"_all  _bit d" .eos fp" J  "_GINTCLR_rsvd1_rsvd2.eosfx" J  "_all  _bit x" .eos f" J  "_GINTEN_rsvd1_rsvd2.eosf" J  "_all  _bit " .eos f" K  "_GINTFLG_rsvd1_rsvd2.eosf" K  "_all  _bit " .eos f" K ")K8KEK_CMPC_CMPDRKaK_DBCTLpKK _AQCSFRC _rsvd1 .eosf"K "_all _bit ".eos f"K "_OSHTLD_GFRCLD_rsvd1.eosf"K "_all _bit ".eos f"K "_GLD_GLDMODEK_rsvd1_GLDPRD_GLDCNT _rsvd2 .eosf"K "_all _bit ".eos f"K  B#_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosf" K  J#_all  _bit " .eos fB# K  #_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosfJ# L  #_all  _bit J# .eos f# L  #_GPIO0_GPIO1_GPIO2_GPIO3 _GPIO4_GPIO5_GPIO6_GPIO7.eosf# L  #_all  _bit # .eos f# +L  #_GPIO8_GPIO9_GPIO10_GPIO11 _GPIO12_GPIO13_GPIO14_GPIO15.eosf# :L  #_all  _bit # .eos f# HL  #_GPIO16_GPIO17_GPIO18_GPIO19 _GPIO20_GPIO21_GPIO22_GPIO23.eosf# WL  #_all  _bit # .eos f# eL  #_GPIO24_GPIO25_GPIO26_GPIO27 _GPIO28_GPIO29_GPIO30_GPIO31.eosf# tL  $_all  _bit # .eos f# L  $LLLL.eosf$ L  $_all  _bit $ .eos f$ L  ^$_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosf$ L  f$_all  _bit $ .eos f^$ L  $_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosff$ L  $_all  _bit f$ .eos f$ L  $_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5 _GPIO6 _GPIO7_GPIO8_GPIO9_GPIO10_GPIO11_GPIO12_GPIO13_GPIO14_GPIO15.eosf$ M  $_all  _bit $ .eos f$ M  %_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21 _GPIO22 _GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosf$ #M  %_all  _bit $ .eos f% 1M  N%_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosf % >M  V%_all  _bit  % .eos fN% JM  %_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosfV% XM  %_all  _bit V% .eos f% eM  %_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5 _GPIO6 _GPIO7_GPIO8_GPIO9_GPIO10_GPIO11_GPIO12_GPIO13_GPIO14_GPIO15.eosf% sM  %_all  _bit % .eos f% M  %_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21 _GPIO22 _GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosf% M  %_all  _bit % .eos f% M  >&_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosf% M  F&_all  _bit % .eos f>& M  &_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosfF& M  &_all  _bit F& .eos f& M  &_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5 _GPIO6 _GPIO7_GPIO8_GPIO9_GPIO10_GPIO11_GPIO12_GPIO13_GPIO14_GPIO15.eosf& M  &_all  _bit & .eos f& M  &_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21 _GPIO22 _GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosf& M  &_all  _bit & .eos f& N  .'_GPIO0_GPIO1_GPIO2_GPIO3_GPIO4_GPIO5_GPIO6_GPIO7_GPIO8_GPIO9 _GPIO10 _GPIO11 _GPIO12 _GPIO13 _GPIO14_GPIO15_GPIO16_GPIO17_GPIO18_GPIO19_GPIO20_GPIO21_GPIO22_GPIO23_GPIO24_GPIO25_GPIO26_GPIO27_GPIO28_GPIO29_GPIO30_GPIO31.eosf& N  6'_all  _bit & .eos f.' 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S_RCERC0_RCERD@_XCERCP_XCERD`_RCEREp_RCERF_XCERE_XCERF_RCERG_RCERH_XCERG_XCERH_rsvd1>@_MFFINT0 H.eosfI@r  :J_CPUREADnnnrrr_rsvd1_rsvd2_rsvd3 _rsvd4 _rsvd5.eosfJ r  BJ_all  _bit J .eos f:J s  ^J_CPUREADnnnrrr_rsvd1_rsvd2_rsvd3 _rsvd4 _rsvd5.eosfBJ s  fJ_all  _bit BJ .eos f^J s  J_CPUREADnnnrrr_rsvd1_rsvd2_rsvd3 _rsvd4 _rsvd5.eosffJ .s  J_all  _bit fJ .eos fJ =s  J_CPUREADnnnrrr_rsvd1_rsvd2_rsvd3 _rsvd4 _rsvd5.eosfJ Ks  J_all  _bit J .eos fJ Xs J_NMIE_rsvd1.eosfJes J_all _bit J.eos fJqs J_NMIINTssssss_rsvd1_rsvd2s s _OVF _rsvd3 .eosfJs J_all _bit J.eos fJs K_rsvd1ssssss_rsvd2_rsvd3s s _OVF _rsvd4 .eosfJt  K_all _bit J.eos fKt (K_NMIINTssssss_rsvd1_rsvd2s s _rsvd3 _rsvd4 .eosf Kt 0K_all _bit  K.eos f(K+t NK_rsvd1ssssss_rsvd2_rsvd3s s _OVF _rsvd4 .eosf0K;t VK_all _bit 0K.eos fNKJt phK_NMICFG J_NMIFLG (K\t Jgt0 Krt@|tPt` NK.eosfVKpt  K_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfhK t  K_all  _bit hK .eos fK t  K_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfK t  K_all  _bit K .eos fK t  L_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfK u  L_all  _bit K .eos fL "u  0L_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosf L ;u  8L_all  _bit  L .eos f0L Su  \L_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosf8L mu  dL_all  _bit 8L .eos f\L u  L_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfdL u  L_all  _bit dL .eos fL u  L_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfL u  L_all  _bit L .eos fL u  M_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfL u  M_all  _bit L .eos fM v  LM_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfM .v  TM_all  _bit M .eos fLM Dv  xM_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfTM ]v  M_all  _bit TM .eos fxM uv  M_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfM v  M_all  _bit M .eos fM v  M_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfM v  M_all  _bit M .eos fM v  N_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfM v  $N_all  _bit M .eos fN w  HN_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosf$N w  PN_all  _bit $N .eos fHN 9w  N_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfPN Pw  N_all  _bit PN .eos fN fw  N_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfN w  N_all  _bit N .eos fN w  N_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfN w  N_all  _bit N .eos fN w  8O_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfN w  @O_all  _bit N .eos f8O w  dO_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosf@O x  lO_all  _bit @O .eos fdO (x  O_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosflO Bx  O_all  _bit lO .eos fO [x  O_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfO rx  O_all  _bit O .eos fO x  P_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfO x  P_all  _bit O .eos fP x  4P_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfP x  @2| 2Q .eosf:Q>|  Q_rsvd1_FAMILY_PARTNOL|.eosf|Q ]|  Q_all  _bit |Q .eos fQ j|  Q_rsvd1_rsvd2_rsvd3_QUALx|_rsvd4 _rsvd5 | _rsvd6|_rsvd7|.eosfQ |  Q_all  _bit Q .eos fQ | Q_CHPEN_OSHTWTH_CHPFREQ_CHPDUTY_rsvd1 .eosfQ| Q_all _bit Q.eos fQ|  Q_CLA1_rsvd1_DMA|||_rsvd2 _HRPWM_rsvd3}}_rsvd4 .eosfQ }  Q_all  _bit Q .eos fQ )}  Q_CAN_A_CAN_B_rsvd1_rsvd2_rsvd3 _rsvd4.eosfQ 8}  R_all  _bit Q .eos fQ F}  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[_all _bit [.eos f[  [‘ϑܑ  _rsvd1 *_rsvd2.eosf[ 7  [_all  _bit [ .eos f[ D  \_DPEI_UOEI_rsvd1_EOWI_EOLI_rsvd2_DPEQ_UOEQ _rsvd3 _EOWQ _EOLQ _rsvd4 _rsvd5.eosf[ S  \_all  _bit [ .eos f\ a *\_rsvd1_RWDLEN1_RFRLEN1_rsvd2.eosf\l 2\_all _bit \.eos f*\v B\_RDATDLY_RFIG_RWDLEN2_RFRLEN2_RPHASE.eosf2\ J\_all _bit 2\.eos fB\  X\_FR_BE.eosfJ\ ˒  `\_all  _bit J\ .eos fX\ Ւ  ~\_POR_XRSn_WDRSn_rsvd1_HWBISTn_rsvd2_rsvd3 _rsvd4.eosf`\ #  \_all  _bit `\ .eos f~\ -  \?_rsvd1_rsvd2.eosf\ J  \_all  _bit \ .eos f\ [  \n_rsvd1_rsvd2.eosf\ y  \_all  _bit \ .eos f\   \ \ .eosf\   \ \ .eosf\ Γ \_CPU2RESܓ_rsvd1 .eosf\ \_all _bit \.eos f\ \_SCICHAR$3>_PARITYI_rsvd1.eosf\S \_all _bit \.eos f\_ \_RXENA_TXENA_SLEEP_TXWAKE_rsvd1_SWRESETm_rsvd2 .eosf\z ]_all _bit \.eos f\ ]_rsvd1_TXEMPTY_TXRDY_rsvd2.eosf] ]_all _bit ].eos f] (]_FFTXDLY_rsvd1_CDC _ABDCLR_ABD.eosf]Ɣ 0]_all _bit ].eos f(]Ӕ D]_RXFFILee_RXFFINT_RXFFST _RXFFOVF.eosf0] L]_all _bit 0].eos fD] `]_TXFFIL7eAe_TXFFINT_TXFFST #_SCIRST.eosfL]- h]_all _bit L].eos f`]: p]_BAUD_rsvd1.eosfh]I x]_all _bit h].eos fp]W ]_BAUD_rsvd1.eosfx]f ]_all _bit x].eos f]t ]_rsvd1F*_rsvd2_rsvd3.eosf] ]_all _bit ].eos f] ]_SAR_rsvd1_SCIFFPE_SCIFFFE.eosf] ]_all _bit ].eos f] ]_ERXDT_rsvd1.eosf] ]_all _bit ].eos f]Ǖ ]_rsvd1_RXWAKE_PE_OE_FE_BRKDT_RXRDY_RXERROR_rsvd2.eosf]Օ ]_all _bit ].eos f] ]_TXDT_rsvd1.eosf] ]_all _bit ].eos f] ^_SCICCR \_SCICTL1 \ p]0 ]_SCICTL2@ ]_SCIRXSTP ]` ]'p ]_rsvd11 ]_SCIFFTX `]_SCIFFRX D]_SCIFFCT (]_rsvd2> _SCIPRI ].eosf]; ^F_WDENINT_WDINTS_rsvd1 .eosf^R $^_all _bit ^.eos f^\ ,^_HLT_rsvd1.eosf$^j 4^_all _bit $^.eos f,^w <^_HLT_rsvd1.eosf4^ D^_all _bit 4^.eos f<^ L^_HLT_rsvd1.eosfD^ T^_all _bit D^.eos fL^ \^_HLT_rsvd1.eosfT^ d^_all _bit T^.eos f\^Ȗ l^_LLT_rsvd1.eosfd^֖ t^_all _bit d^.eos fl^ |^_LLT_rsvd1.eosft^ ^_all _bit t^.eos f|^ ^_LLT_rsvd1.eosf^ ^_all _bit ^.eos f^ ^_LLT_rsvd1.eosf^' ^_all _bit ^.eos f^4 ^_COSR_IEH_IEL_CS1_CS0_MFIE _rsvd1 .eosf^C ^_all _bit ^.eos f^Q ^_COSR_IEH_IEL_CS1_CS0_MFIE _rsvd1 .eosf^` ^_all _bit ^.eos f^n ^_COSR_IEH_IEL_CS1_CS0_MFIE _rsvd1 .eosf^} ^_all _bit ^.eos f^ ^_COSR_IEH_IEL_CS1_CS0_MFIE _rsvd1 .eosf^ __all _bit ^.eos f^ __MOD_rsvd1_rsvd2_rsvd3_MS .eosf_ __all _bit _.eos f_ɗ (__MOD_rsvd1_rsvd2_rsvd3_MS .eosf_ڗ 0__all _bit _.eos f(_ >__MOD_rsvd1_rsvd2_rsvd3_MS .eosf0_ F__all _bit 0_.eos f>_  T__MOD_rsvd1_rsvd2_rsvd3_MS .eosfF_ \__all _bit F_.eos fT_, h__rsvd1 _MIE _rsvd2_rsvd3.eosf\_8 p__all _bit \_.eos fh_C  x__DATA16Q.eosfp_ [  __all  _bit p_ .eos fx_ h  __DATA16Q.eosf_ v  __all  _bit _ .eos f_   __DATA16Q.eosf_  __all  _bit _ .eos f_   __DATA16Q.eosf_  __all  _bit _ .eos f_  __DOSR_FEN_AE _SST ɘ _rsvd1 .eosf_Ә __all _bit _.eos f_ __DOSR_FEN_AE _SST ɘ _rsvd1 .eosf_ __all _bit _.eos f_ __DOSR_FEN_AE _SST ɘ _rsvd1 .eosf_ __all _bit _.eos f_  `_DOSR_FEN_AE _SST ɘ _rsvd1 .eosf_0 `_all _bit _.eos f`? b`_SDIFLG ` J ` _SDCTL@ h__rsvd1PU` 6a_p a_rsvd2>i _u _  `_SDCMPH10 ,^_SDCMPL1@ l^P ^_SDDATA1` x_ _rsvd3> (_ _  `_SDCMPH20 <^_SDCMPL2@ |^P ^_SDDATA2` _ _rsvd4> >_˙ _֙  a_SDCMPH30 L^_SDCMPL3@ ^P ^_SDDATA3` _ _rsvd5> T_ `  a_SDCMPH40 \^_SDCMPL4@ ^ P ^_SDDATA4` _ _rsvd6>8.eosf`  `_IFH1_IFL1_IFH2_IFL2_IFH3_IFL3_IFH4_IFL4_MF1_MF2 _MF3 _MF4 _AF1 _AF2 _AF3_AF4_rsvd1_MIF.eosfb` %  `_all  _bit b` .eos f` 4  `_IFH1_IFL1_IFH2_IFL2_IFH3_IFL3_IFH4_IFL4_MF1_MF2 _MF3 _MF4 _AF1 _AF2 _AF3_AF4_rsvd1_MIF.eosf` A  `_all  _bit ` .eos f` M `_rsvd1_rsvd2_rsvd3_rsvd4 _DR _SH .eosf`\ `_all _bit `.eos f`j `_rsvd1_rsvd2_rsvd3_rsvd4 _DR _SH .eosf`y `_all _bit `.eos f` a_rsvd1_rsvd2_rsvd3_rsvd4 _DR _SH .eosf`  a_all _bit `.eos fa a_rsvd1_rsvd2_rsvd3_rsvd4 _DR _SH .eosf a "a_all _bit  a.eos fa 6a_rsvd1_rsvd2_rsvd3_rsvd4 _rsvd5 _MFE _rsvd6 _rsvd7 .eosf"aК >a_all _bit "a.eos f6aޚ  ha_rsvd1_IBANK_rsvd2_CL _rsvd3 _rsvd4 _NM_rsvd5_rsvd6_rsvd7_rsvd8_rsvd9_rsvd10_rsvd11_PDWR_PD_SR.eosf>a   pa_all  _bit >a .eos fha   |a$ _rsvd1 _rsvd2_rsvd3 .eosfpa 2  a_all  _bit pa .eos f|a A  a_rsvd1_T_RRD_rsvd2_T_RC_T_RAS _T_WR_rsvd3_T_RCD_rsvd4_T_RP_T_RFC.eosfa P  a_all  _bit a .eos fa ^  a_T_XS_rsvd1 _rsvd2.eosfa q  a_all  _bit a .eos fa  a_rsvd1_MAF1_MAF2 _MAF3 _MAF4 _MAL1 _MAL2 _MAL3_MAL4.eosfa a_all _bit a.eos fa  a_PF1SEL_PF2SEL_rsvd1_rsvd2_rsvd3_rsvd4 _rsvd5 _rsvd6_rsvd7.eosfa  a_all  _bit a .eos fa   bʛ؛  ,:HVdr_rsvd1.eosfa  b_all  _bit a .eos fb   8b_TASK1_TASK2_TASK3_TASK4_TASK5_TASK6_TASK7_TASK8_rsvd1_rsvd2.eosf b  @b_all  _bit  b .eos f8b ɜ  Xb_TASK1_TASK2_TASK3_TASK4_TASK5_TASK6_TASK7_TASK8_rsvd1_rsvd2.eosf@b ڜ  `b_all  _bit @b .eos fXb   pb1_rsvd12_rsvd2_rsvd3 _rsvd4.eosf`b  xb_all  _bit `b .eos fpb   b_McBSP_A_McBSP_B_rsvd1_USB_A_rsvd2_rsvd3.eosfxb   b_all  _bit xb .eos fb *  b_ADC_A_ADC_B_ADC_C_ADC_D_rsvd1 _rsvd2.eosfb ;  b_all  _bit b .eos fb K  b_CMPSS1_CMPSS2_CMPSS3_CMPSS4_CMPSS5_CMPSS6_CMPSS7_CMPSS8_rsvd1_rsvd2.eosfb \  b_all  _bit b .eos fb l  b_rsvd1_rsvd2_rsvd3_rsvd4_rsvd5 _DAC_A_DAC_B_DAC_C_rsvd6_rsvd7 .eosfb }  b_all  _bit b .eos fb   b_EMIF1_EMIF2_rsvd1_rsvd2.eosfb  b_all  _bit b .eos fb   "c_EPWM1_EPWM2_EPWM3_EPWM4_EPWM5_EPWM6_EPWM7_EPWM8_EPWM9_EPWM10 _EPWM11 _EPWM12 _rsvd1 _rsvd2 _rsvd3_rsvd4_rsvd5.eosfb  *c_all  _bit b .eos f"c ˝  Bc_ECAP1_ECAP2_ECAP3_ECAP4_ECAP5_ECAP6_rsvd1_rsvd2_rsvd3_rsvd4.eosf*c ۝  Jc_all  _bit *c .eos fBc   Zc_EQEP1_EQEP2_EQEP3_rsvd1_rsvd2 _rsvd3.eosfJc  bc_all  _bit Jc .eos fZc   zc_rsvd1_rsvd2_rsvd3_rsvd4_rsvd5_rsvd6_rsvd7_rsvd8_rsvd9_rsvd10.eosfbc   c_all  _bit bc .eos fzc (  c_SD1_SD2_rsvd1_rsvd2_rsvd3_rsvd4_rsvd5_rsvd6_rsvd7_rsvd8.eosfc 8  c_all  _bit c .eos fc G  c_SCI_A_SCI_B_SCI_C_SCI_D_rsvd1 _rsvd2.eosfc W  c_all  _bit c .eos fc f  c_SPI_A_SPI_B_SPI_C_rsvd1_rsvd2 _rsvd3_rsvd4_rsvd5.eosfc v  c_all  _bit c .eos fc   c_I2C_A_I2C_B_rsvd1_rsvd2_rsvd3_rsvd4.eosfc  c_all  _bit c .eos fc  d_RRST_RRDY_RFULL_RINTM_rsvd1_DXENA_rsvd2_CLKSTP _RJUST _DLB.eosfc d_all _bit c.eos fdŞ (d_XRST_XRDY_XEMPTYў_XINTM_GRST_FRST_SOFT_FREE _rsvd1 .eosfd۞ 0d_all _bit d.eos f(d 8d_rsvd1 .eosf0d @d_all _bit 0d.eos f8d  Pd_SPICHAR_SPILBK_rsvd1'_rsvd2.eosf@d3 Xd_all _bit @d.eos fPd? hdL_TALKWep_rsvd1 .eosfXd pd_all _bit Xd.eos fhd xd_TXDLY_rsvd1.eosfpd d_all _bit pd.eos fxd d_RXFFILee_RXFFINT_RXFFST _RXFFOVF.eosfd d_all _bit d.eos fd͟ d_TXFFIL7eAe_TXFFINT_TXFFST_TXFIFO ۟_SPIRST.eosfd d_all _bit d.eos fd d_TRIWIRE_STEINV_rsvd1_FREE_SOFT_rsvd2 .eosfd d_all _bit d.eos fd d_rsvd1"0:_rsvd2.eosfdH d_all _bit d.eos fdT  e_SPICCR Pd_SPICTL hd_SPISTS d_rsvd10_SPIBRR@ 8d_rsvd2P^`hpr_SPIDAT_SPIFFTX d_SPIFFRX d_SPIFFCT xd_rsvd3> _SPIPRI d.eosfd| e_CLKGDV_FWID.eosf e e_all _bit  e.eos fe (e_FPER _FSGM _CLKSM _rsvd1_GSYNC.eosfe 0e_all _bit e.eos f(e  FeȠՠ  _rsvd1_rsvd2 _SYNCOUT_rsvd3.eosf0e  Ne_all  _bit 0e .eos fFe   Ze+_rsvd1_rsvd2.eosfNe <  be_all  _bit Ne .eos fZe M  le`_rsvd1 _rsvd2.eosfbe n  te_all  _bit be .eos fle   e_PLLEN _rsvd1_rsvd2.eosfte  e_all  _bit te .eos fe   e_IMULT_rsvd1_FMULT_rsvd2 _rsvd3.eosfe  e_all  _bit e .eos fe ¡  e_LOCKS_SLIPS_rsvd1_rsvd2.eosfe ҡ  e_all  _bit e .eos fe  e_rsvd1 _rsvd2 .eosfe* e_all _bit e.eos fe6 e_CTRMODE_PHSEN_PRDLDB_SWFSYNCL_CLKDIV _PHSDIR ;.eosfeW e_all _bit e.eos feb  e_TBPHSHR_TBPHS.eosfe n  e_all  _bit e .eos fe y f_CTRDIR_SYNCI_CTRMAX_rsvd1 .eosfe f_all _bit e.eos ff $f_rsvd1_TSS_TRB_rsvd2_SOFT _FREE _rsvd3 _TIE_TIF.eosff_TCR_REG ,f_all _bit f.eos f$f  @f_RDSIZEI_rsvd1_RDSIZEQ_rsvd2 _TXSIZEA_rsvd3_rsvd4_rsvd5.eosf,f  Hf_all  _bit ,f .eos f@f   Pf_LSW_MSW.eosfHf _TIM_REG  Xf_all  _bit Hf .eos fPf   df̢ۢ_rsvd1 _rsvd2.eosfXf  lf_all  _bit Xf .eos fdf  tf_TDDRH_PSCH.eosflf |f_all _bit lf.eos ftf f_TDDR_PSC.eosf|f_TPR_REG f_all _bit |f.eos ff `f Fe +  &@ Ze .eosff`3  f_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosff K  f_all  _bit f .eos ff b  f_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosff {  f_all  _bit f .eos ff   2g_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosff  :g_all  _bit f .eos f2g   ^g_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosf:g ֣  fg_all  _bit :g .eos f^g   g_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosffg   g_all  _bit fg .eos fg   g_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfg 4  g_all  _bit g .eos fg I  h_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfg a  h_all  _bit g .eos fh x  .h_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosf h  6h_all  _bit  h .eos f.h   zh_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosf6h  h_all  _bit 6h .eos fzh Ԥ  h_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfh  h_all  _bit h .eos fh   h_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfh   h_all  _bit h .eos fh 0  i_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfh E  &i_all  _bit h .eos fi Y  Ji_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosf&i p  Ri_all  _bit &i .eos fJi   vi_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfRi  ~i_all  _bit Ri .eos fvi   i_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosf~i ʥ  i_all  _bit ~i .eos fi ޥ  i_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfi  i_all  _bit i .eos fi   j_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfi #  "j_all  _bit i .eos fj :  fj_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosf"j O  nj_all  _bit "j .eos ffj c  j_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfnj z  j_all  _bit nj .eos fj   j_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfj  j_all  _bit j .eos fj   k_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfj Ԧ  k_all  _bit j .eos f k   6k_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5 _MUX6 _MUX7_MUX8_MUX9_MUX10_MUX11_MUX12_MUX13_MUX14_MUX15.eosfk  >k_all  _bit k .eos f6k   bk_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21 _MUX22 _MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosf>k -  jk_all  _bit >k .eos fbk D  k_MUX0_MUX1_MUX2_MUX3_MUX4_MUX5_MUX6_MUX7_MUX8_MUX9 _MUX10 _MUX11 _MUX12 _MUX13 _MUX14_MUX15_MUX16_MUX17_MUX18_MUX19_MUX20_MUX21_MUX22_MUX23_MUX24_MUX25_MUX26_MUX27_MUX28_MUX29_MUX30_MUX31.eosfjk Y  k_all  _bit jk .eos fk m  k_LOCK_rsvd1_KEY.eosfk |  k_all  _bit k .eos fk   k_TRIP4_TRIP5_TRIP7_TRIP8_TRIP9_TRIP10_TRIP11_TRIP12_rsvd1_rsvd2.eosfk  k_all  _bit k .eos fk  k_ENABLE_rsvd1.eosfk k_all _bit k.eos fkƧ l_CBC1_CBC2_CBC3_CBC4_CBC5_CBC6_DCAEVT2_DCBEVT2_rsvd1.eosfkէ l_all _bit k.eos fl ,l_CBC1_CBC2_CBC3_CBC4_CBC5_CBC6_DCAEVT2_DCBEVT2_rsvd1.eosfl 4l_all _bit l.eos f,l Jl_INT_CBC_OST_DCAEVT1_DCAEVT2_DCBEVT1_DCBEVT2_rsvd1 .eosf4l Rl_all _bit 4l.eos fJl! bl_TZAU_TZAD_TZBU_TZBD _rsvd1 _ETZE.eosfRl. jl_all _bit Rl.eos fbl: xlIS]g _rsvd1 .eosfjlq l_all _bit jl.eos fxl l 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CPU1.c_SourceAddr_SourceEndAddr_DestAddrF2837xD_CodeStartBranch.asmWD_DISABLEwd_disableF2837xD_DefaultISR.c_XINT5_ISR_XINT4_ISR_XINT3_ISR_XINT2_ISR_XINT1_ISR_WAKE_ISR_USER9_ISR_USER8_ISR_USER7_ISR_USER6_ISR_USER5_ISR_USER4_ISR_USER3_ISR_USER2_ISR_USER1_ISR_USER12_ISR_USER11_ISR_USER10_ISR_USBA_ISR_UPPA_ISR_TIMER2_ISR_TIMER1_ISR_TIMER0_ISR_SYS_PLL_SLIP_ISR_SPIC_TX_ISR_SPIC_RX_ISR_SPIB_TX_ISR_SPIB_RX_ISR_SPIA_TX_ISR_SPIA_RX_ISR_SCID_TX_ISR_SCID_RX_ISR_SCIC_TX_ISR_SCIC_RX_ISR_SCIB_TX_ISR_SCIB_RX_ISR_SCIA_TX_ISR_SCIA_RX_ISR_RTOS_ISR_RAM_CORRECTABLE_ERROR_ISR_RAM_ACCESS_VIOLATION_ISR_PIE_RESERVED_ISR_NOTUSED_ISR_MCBSPB_TX_ISR_MCBSPB_RX_ISR_MCBSPA_TX_ISR_MCBSPA_RX_ISR_IPC3_ISR_IPC2_ISR_IPC1_ISR_IPC0_ISR_ILLEGAL_ISR_I2CB_ISR_I2CB_FIFO_ISR_I2CA_ISR_I2CA_FIFO_ISR_FPU_UNDERFLOW_ISR_FPU_OVERFLOW_ISR_FLASH_CORRECTABLE_ERROR_ISR_EQEP3_ISR_EQEP2_ISR_EQEP1_ISR_EPWM9_TZ_ISR_EPWM9_ISR_EPWM8_TZ_ISR_EPWM8_ISR_EPWM7_TZ_ISR_EPWM7_ISR_EPWM6_TZ_ISR_EPWM6_ISR_EPWM5_TZ_ISR_EPWM5_ISR_EPWM4_TZ_ISR_EPWM4_ISR_EPWM3_TZ_ISR_EPWM3_ISR_EPWM2_TZ_ISR_EPWM2_ISR_EPWM1_TZ_ISR_EPWM1_ISR_EPWM12_TZ_ISR_EPWM12_ISR_EPWM11_TZ_ISR_EPWM11_ISR_EPWM10_TZ_ISR_EPWM10_ISR_EMPTY_ISR_EMIF_ERROR_ISR_ECAP6_ISR_ECAP5_ISR_ECAP4_ISR_ECAP3_ISR_ECAP2_ISR_ECAP1_ISR_DMA_CH6_ISR_DMA_CH5_ISR_DMA_CH4_ISR_DMA_CH3_ISR_DMA_CH2_ISR_DMA_CH1_ISR_DCANB_2_ISR_DCANB_1_ISR_DCANA_2_ISR_DCANA_1_ISR_DATALOG_ISR_CLA_UNDERFLOW_ISR_CLA_OVERFLOW_ISR_CLA1_8_ISR_CLA1_7_ISR_CLA1_6_ISR_CLA1_5_ISR_CLA1_4_ISR_CLA1_3_ISR_CLA1_2_ISR_CLA1_1_ISR_AUX_PLL_SLIP_ISR_ADCD_EVT_ISR_ADCD4_ISR_ADCD3_ISR_ADCD2_ISR_ADCD1_ISR_ADCC_EVT_ISR_ADCC4_ISR_ADCC3_ISR_ADCC2_ISR_ADCC1_ISR_ADCB_EVT_ISR_ADCB4_ISR_ADCB3_ISR_ADCB2_ISR_ADCB1_ISR_ADCA_EVT_ISR_ADCA4_ISR_ADCA3_ISR_ADCA2_ISR_ADCA1_ISR.text:retainF2837xD_GlobalVariableDefs.c_ACCESS_PROTECTION_REGS_NMAVINTEN_NMCPURDAVADDR_NMCPUWRAVADDR_NMCPUFAVADDR_NMDMAWRAVADDR_NMCLA1RDAVADDR_NMCLA1WRAVADDR_NMCLA1FAVADDR_MAVINTEN_MCPUFAVADDR_MCPUWRAVADDR_MDMAWRAVADDR_ADCBURSTCTL_BITS_BURSTTRIGSEL_BURSTSIZE_ADCBURSTCTL_REG_ADCCOUNTER_BITS_FREECOUNT_ADCCOUNTER_REG_ADCCTL1_BITS_INTPULSEPOS_ADCPWDNZ_ADCBSYCHN_ADCCTL1_REG_ADCCTL2_BITS_PRESCALE_RESOLUTION_SIGNALMODE_ADCCTL2_REG_ADCEVTCLR_BITS_PPB1TRIPHI_PPB1TRIPLO_PPB1ZERO_PPB2TRIPHI_PPB2TRIPLO_PPB2ZERO_PPB3TRIPHI_PPB3TRIPLO_PPB3ZERO_PPB4TRIPHI_PPB4TRIPLO_PPB4ZERO_ADCEVTCLR_REG_ADCEVTINTSEL_BITS_ADCEVTINTSEL_REG_ADCEVTSEL_BITS_ADCEVTSEL_REG_ADCEVTSTAT_BITS_ADCEVTSTAT_REG_ADCINTFLGCLR_BITS_ADCINTFLGCLR_REG_ADCINTFLG_BITS_ADCINTFLG_REG_ADCINTOVFCLR_BITS_ADCINTOVFCLR_REG_ADCINTOVF_BITS_ADCINTOVF_REG_ADCINTSEL1N2_BITS_INT1CONT_INT2CONT_ADCINTSEL1N2_REG_ADCINTSEL3N4_BITS_INT3CONT_INT4CONT_ADCINTSEL3N4_REG_ADCINTSOCSEL1_BITS_ADCINTSOCSEL1_REG_ADCINTSOCSEL2_BITS_ADCINTSOCSEL2_REG_ADCOFFTRIM_BITS_ADCOFFTRIM_REG_ADCPPB1CONFIG_BITS_TWOSCOMPEN_ADCPPB1CONFIG_REG_ADCPPB1OFFCAL_BITS_ADCPPB1OFFCAL_REG_ADCPPB1RESULT_BITS_PPBRESULT_ADCPPB1RESULT_REG_ADCPPB1STAMP_BITS_DLYSTAMP_ADCPPB1STAMP_REG_ADCPPB1TRIPHI_BITS_ADCPPB1TRIPHI_REG_ADCPPB1TRIPLO_BITS_REQSTAMP_ADCPPB1TRIPLO_REG_ADCPPB2CONFIG_BITS_ADCPPB2CONFIG_REG_ADCPPB2OFFCAL_BITS_ADCPPB2OFFCAL_REG_ADCPPB2RESULT_BITS_ADCPPB2RESULT_REG_ADCPPB2STAMP_BITS_ADCPPB2STAMP_REG_ADCPPB2TRIPHI_BITS_ADCPPB2TRIPHI_REG_ADCPPB2TRIPLO_BITS_ADCPPB2TRIPLO_REG_ADCPPB3CONFIG_BITS_ADCPPB3CONFIG_REG_ADCPPB3OFFCAL_BITS_ADCPPB3OFFCAL_REG_ADCPPB3RESULT_BITS_ADCPPB3RESULT_REG_ADCPPB3STAMP_BITS_ADCPPB3STAMP_REG_ADCPPB3TRIPHI_BITS_ADCPPB3TRIPHI_REG_ADCPPB3TRIPLO_BITS_ADCPPB3TRIPLO_REG_ADCPPB4CONFIG_BITS_ADCPPB4CONFIG_REG_ADCPPB4OFFCAL_BITS_ADCPPB4OFFCAL_REG_ADCPPB4RESULT_BITS_ADCPPB4RESULT_REG_ADCPPB4STAMP_BITS_ADCPPB4STAMP_REG_ADCPPB4TRIPHI_BITS_ADCPPB4TRIPHI_REG_ADCPPB4TRIPLO_BITS_ADCPPB4TRIPLO_REG_ADCREV_BITS_ADCREV_REG_ADCSOC0CTL_BITS_ADCSOC0CTL_REG_ADCSOC10CTL_BITS_ADCSOC10CTL_REG_ADCSOC11CTL_BITS_ADCSOC11CTL_REG_ADCSOC12CTL_BITS_ADCSOC12CTL_REG_ADCSOC13CTL_BITS_ADCSOC13CTL_REG_ADCSOC14CTL_BITS_ADCSOC14CTL_REG_ADCSOC15CTL_BITS_ADCSOC15CTL_REG_ADCSOC1CTL_BITS_ADCSOC1CTL_REG_ADCSOC2CTL_BITS_ADCSOC2CTL_REG_ADCSOC3CTL_BITS_ADCSOC3CTL_REG_ADCSOC4CTL_BITS_ADCSOC4CTL_REG_ADCSOC5CTL_BITS_ADCSOC5CTL_REG_ADCSOC6CTL_BITS_ADCSOC6CTL_REG_ADCSOC7CTL_BITS_ADCSOC7CTL_REG_ADCSOC8CTL_BITS_ADCSOC8CTL_REG_ADCSOC9CTL_BITS_ADCSOC9CTL_REG_ADCSOCFLG1_BITS_ADCSOCFLG1_REG_ADCSOCFRC1_BITS_ADCSOCFRC1_REG_ADCSOCOVF1_BITS_ADCSOCOVF1_REG_ADCSOCOVFCLR1_BITS_ADCSOCOVFCLR1_REG_ADCSOCPRICTL_BITS_SOCPRIORITY_RRPOINTER_ADCSOCPRICTL_REG_ADC_REGS_ADCBURSTCTL_ADCINTFLG_ADCINTFLGCLR_ADCINTOVF_ADCINTOVFCLR_ADCINTSEL1N2_ADCINTSEL3N4_ADCSOCPRICTL_ADCINTSOCSEL1_ADCINTSOCSEL2_ADCSOCFLG1_ADCSOCFRC1_ADCSOCOVF1_ADCSOCOVFCLR1_ADCSOC0CTL_ADCSOC1CTL_ADCSOC2CTL_ADCSOC3CTL_ADCSOC4CTL_ADCSOC5CTL_ADCSOC6CTL_ADCSOC7CTL_ADCSOC8CTL_ADCSOC9CTL_ADCSOC10CTL_ADCSOC11CTL_ADCSOC12CTL_ADCSOC13CTL_ADCSOC14CTL_ADCSOC15CTL_ADCEVTSTAT_ADCEVTCLR_ADCEVTSEL_ADCEVTINTSEL_ADCCOUNTER_ADCOFFTRIM_ADCPPB1CONFIG_ADCPPB1STAMP_ADCPPB1OFFCAL_ADCPPB1OFFREF_ADCPPB1TRIPHI_ADCPPB1TRIPLO_ADCPPB2CONFIG_ADCPPB2STAMP_ADCPPB2OFFCAL_ADCPPB2OFFREF_ADCPPB2TRIPHI_ADCPPB2TRIPLO_ADCPPB3CONFIG_ADCPPB3STAMP_ADCPPB3OFFCAL_ADCPPB3OFFREF_ADCPPB3TRIPHI_ADCPPB3TRIPLO_ADCPPB4CONFIG_ADCPPB4STAMP_ADCPPB4OFFCAL_ADCPPB4OFFREF_ADCPPB4TRIPHI_ADCPPB4TRIPLO_ADCINLTRIM1_ADCINLTRIM2_ADCINLTRIM3_ADCINLTRIM4_ADCINLTRIM5_ADCINLTRIM6_ADC_RESULT_REGS_ADCRESULT0_ADCRESULT1_ADCRESULT2_ADCRESULT3_ADCRESULT4_ADCRESULT5_ADCRESULT6_ADCRESULT7_ADCRESULT8_ADCRESULT9_ADCRESULT10_ADCRESULT11_ADCRESULT12_ADCRESULT13_ADCRESULT14_ADCRESULT15_ADCPPB1RESULT_ADCPPB2RESULT_ADCPPB3RESULT_ADCPPB4RESULT_ANALOG_SUBSYS_REGS_INTOSC1TRIM_INTOSC2TRIM_ANAREFTRIMA_ANAREFTRIMB_ANAREFTRIMC_ANAREFTRIMD_ANAREFTRIMA_BITS_BGVALTRIM_BGSLOPETRIM_IREFTRIM_ANAREFTRIMA_REG_ANAREFTRIMB_BITS_ANAREFTRIMB_REG_ANAREFTRIMC_BITS_ANAREFTRIMC_REG_ANAREFTRIMD_BITS_ANAREFTRIMD_REG_AQCSFRC_BITS_AQCSFRC_REG_AQCTLA2_BITS_AQCTLA2_REG_AQCTLA_BITS_AQCTLA_REG_AQCTLB2_BITS_AQCTLB2_REG_AQCTLB_BITS_AQCTLB_REG_AQCTL_BITS_LDAQAMODE_LDAQBMODE_SHDWAQAMODE_SHDWAQBMODE_LDAQASYNC_LDAQBSYNC_AQCTL_REG_AQSFRC_BITS_AQSFRC_REG_AQTSRCSEL_BITS_AQTSRCSEL_REG_ASYNC_CS2_CR_BITS_R_STROBE_W_STROBE_ASYNC_CS2_CR_REG_ASYNC_CS3_CR_BITS_ASYNC_CS3_CR_REG_ASYNC_CS4_CR_BITS_ASYNC_CS4_CR_REG_ASYNC_WCCR_BITS_MAX_EXT_WAIT_ASYNC_WCCR_REG_AUXCLKDIVSEL_BITS_AUXPLLDIV_AUXCLKDIVSEL_REG_AUXPLLCTL1_BITS_PLLCLKEN_AUXPLLCTL1_REG_AUXPLLMULT_BITS_AUXPLLMULT_REG_AUXPLLSTS_BITS_AUXPLLSTS_REG_BURST_COUNT_BITS_BURSTCOUNT_BURST_COUNT_REG_BURST_SIZE_BITS_BURST_SIZE_REG_CEINTCLR_BITS_CEINTCLR_CEINTCLR_REG_CEINTEN_BITS_CEINTEN_REG_CEINTFLG_BITS_CEINTFLAG_CEINTFLG_REG_CEINTSET_BITS_CEINTSET_CEINTSET_REG_CERRCLR_BITS_CPURDERR_DMARDERR_CLA1RDERR_CERRCLR_REG_CERRFLG_BITS_CERRFLG_REG_CERRSET_BITS_CERRSET_REG_CHCTL_BITS_SDRTXILA_CHCTL_REG_CHIDESC1_BITS_CHIDESC1_REG_CHIDESC2_BITS_CHIDESC2_REG_CHIST1_BITS_CHIST1_REG_CHIST2_BITS_CHIST2_REG_CHQDESC1_BITS_CHQDESC1_REG_CHQDESC2_BITS_CHQDESC2_REG_CHQST1_BITS_CHQST1_REG_CHQST2_BITS_CHQST2_REG_BURST_SIZE_BURST_COUNT_SRC_BURST_STEP_DST_BURST_STEP_TRANSFER_SIZE_TRANSFER_COUNT_SRC_TRANSFER_STEP_DST_TRANSFER_STEP_SRC_WRAP_SIZE_SRC_WRAP_COUNT_SRC_WRAP_STEP_DST_WRAP_SIZE_DST_WRAP_COUNT_DST_WRAP_STEP_SRC_BEG_ADDR_SHADOW_SRC_ADDR_SHADOW_SRC_BEG_ADDR_ACTIVE_SRC_ADDR_ACTIVE_DST_BEG_ADDR_SHADOW_DST_ADDR_SHADOW_DST_BEG_ADDR_ACTIVE_DST_ADDR_ACTIVE_CLA1TASKSRCSEL1_BITS_CLA1TASKSRCSEL1_REG_CLA1TASKSRCSEL2_BITS_CLA1TASKSRCSEL2_REG_CLA1TASKSRCSELLOCK_BITS_CLA1TASKSRCSEL1_CLA1TASKSRCSEL2_CLA1TASKSRCSELLOCK_REG_CLA_REGS_MICLROVF_CLA_SOFTINT_REGS_SOFTINTEN_SOFTINTFRC_CLKCFGLOCK1_BITS_CLKSRCCTL1_CLKSRCCTL2_CLKSRCCTL3_SYSPLLCTL1_SYSPLLCTL2_SYSPLLCTL3_SYSPLLMULT_AUXPLLCTL1_AUXPLLMULT_SYSCLKDIVSEL_AUXCLKDIVSEL_PERCLKDIVSEL_CLKCFGLOCK1_REG_CLKSEM_BITS_CLKSEM_REG_CLKSRCCTL1_BITS_OSCCLKSRCSEL_INTOSC2OFF_CLKSRCCTL1_REG_CLKSRCCTL2_BITS_AUXOSCCLKSRCSEL_CANABCLKSEL_CANBBCLKSEL_CLKSRCCTL2_REG_CLKSRCCTL3_BITS_XCLKOUTSEL_CLKSRCCTL3_REG_CLK_CFG_REGS_CLKCFGLOCK1_SYSPLLSTS_AUXPLLSTS_XCLKOUTDIVSEL_CMPA_BITS_CMPA_REG_CMPB_BITS_CMPB_REG_CMPCTL2_BITS_LOADCMODE_LOADDMODE_SHDWCMODE_SHDWDMODE_LOADCSYNC_LOADDSYNC_CMPCTL2_REG_CMPCTL_BITS_LOADAMODE_LOADBMODE_SHDWAMODE_SHDWBMODE_SHDWAFULL_SHDWBFULL_LOADASYNC_LOADBSYNC_CMPCTL_REG_CMPSS_REGS_COMPHYSCTL_COMPSTSCLR_COMPDACCTL_DACHVALS_DACHVALA_RAMPMAXREFA_RAMPMAXREFS_RAMPDECVALA_RAMPDECVALS_DACLVALS_DACLVALA_RAMPDLYA_RAMPDLYS_CTRIPLFILCTL_CTRIPLFILCLKCTL_CTRIPHFILCTL_CTRIPHFILCLKCTL_COMPLOCK_COMPCTL_BITS_COMPHSOURCE_COMPHINV_CTRIPHSEL_CTRIPOUTHSEL_ASYNCHEN_COMPLSOURCE_COMPLINV_CTRIPLSEL_CTRIPOUTLSEL_ASYNCLEN_COMPDACE_COMPCTL_REG_COMPDACCTL_BITS_DACSOURCE_RAMPSOURCE_RAMPLOADSEL_SWLOADSEL_FREESOFT_COMPDACCTL_REG_COMPHYSCTL_BITS_COMPHYSCTL_REG_COMPLOCK_BITS_COMPLOCK_REG_COMPSTSCLR_BITS_HLATCHCLR_HSYNCCLREN_LLATCHCLR_LSYNCCLREN_COMPSTSCLR_REG_COMPSTS_BITS_COMPHSTS_COMPHLATCH_COMPLSTS_COMPLLATCH_COMPSTS_REG_CONTROL_BITS_SOFTRESET_PERINTFRC_PERINTCLR_PERINTFLG_TRANSFERSTS_BURSTSTS_CONTROL_REG_CPU2RESCTL_BITS_CPU2RESCTL_REG_CPUSEL0_BITS_CPUSEL0_REG_CPUSEL11_BITS_CPUSEL11_REG_CPUSEL12_BITS_CPUSEL12_REG_CPUSEL14_BITS_CPUSEL14_REG_CPUSEL1_BITS_CPUSEL1_REG_CPUSEL2_BITS_CPUSEL2_REG_CPUSEL3_BITS_CPUSEL3_REG_CPUSEL4_BITS_CPUSEL4_REG_CPUSEL5_BITS_CPUSEL5_REG_CPUSEL6_BITS_CPUSEL6_REG_CPUSEL7_BITS_CPUSEL7_REG_CPUSEL8_BITS_CPUSEL8_REG_CPUSEL9_BITS_CPUSEL9_REG_CPUSYSLOCK1_BITS_HIBBOOTMODE_IORESTOREADDR_PIEVERRADDR_PCLKCR10_PCLKCR11_PCLKCR12_PCLKCR13_PCLKCR14_PCLKCR15_PCLKCR16_GPIOLPMSEL0_GPIOLPMSEL1_CPUSYSLOCK1_REG_CPUTIMER_REGS_CPU_SYS_REGS_CPUSYSLOCK1_TMR2CLKCTL_CTRIPHFILCLKCTL_BITS_CLKPRESCALE_CTRIPHFILCLKCTL_REG_CTRIPHFILCTL_BITS_CTRIPHFILCTL_REG_CTRIPLFILCLKCTL_BITS_CTRIPLFILCLKCTL_REG_CTRIPLFILCTL_BITS_CTRIPLFILCTL_REG_DACCTL_BITS_DACREFSEL_LOADMODE_DACCTL_REG_DACHVALA_BITS_DACHVALA_REG_DACHVALS_BITS_DACHVALS_REG_DACLOCK_BITS_DACOUTEN_DACLOCK_REG_DACLVALA_BITS_DACLVALA_REG_DACLVALS_BITS_DACLVALS_REG_DACOUTEN_BITS_DACOUTEN_REG_DACREV_BITS_DACREV_REG_DACTRIM_BITS_OFFSET_TRIM_DACTRIM_REG_DACVALA_BITS_DACVALA_REG_DACVALS_BITS_DACVALS_REG_DAC_REGS_DBCTL2_BITS_LOADDBCTLMODE_SHDWDBCTLMODE_DBCTL2_REG_DBCTL_BITS_OUT_MODE_LOADREDMODE_LOADFEDMODE_SHDWDBREDMODE_SHDWDBFEDMODE_DEDB_MODE_HALFCYCLE_DBCTL_REG_DBFEDHR_BITS_DBFEDHR_REG_DBREDHR_BITS_DBREDHR_REG_DC0_BITS_SINGLE_CORE_DC10_BITS_DC10_REG_DC11_BITS_DC11_REG_DC12_BITS_DC12_REG_DC13_BITS_DC13_REG_DC14_BITS_DC14_REG_DC15_BITS_DC15_REG_DC17_BITS_DC17_REG_DC18_BITS_DC18_REG_DC19_BITS_DC19_REG_DC1_BITS_CPU1_FPU_TMU_CPU2_FPU_TMU_CPU1_VCU_CPU2_VCU_CPU1_CLA1_CPU2_CLA1_DC20_BITS_DC20_REG_DC2_BITS_DC3_BITS_DC4_BITS_DC5_BITS_DC6_BITS_DC7_BITS_DC8_BITS_DC9_BITS_DCACTL_BITS_EVT1SRCSEL_EVT1FRCSYNCSEL_EVT1SOCE_EVT1SYNCE_EVT2SRCSEL_EVT2FRCSYNCSEL_DCACTL_REG_DCAHTRIPSEL_BITS_TRIPINPUT1_TRIPINPUT2_TRIPINPUT3_TRIPINPUT4_TRIPINPUT5_TRIPINPUT6_TRIPINPUT7_TRIPINPUT8_TRIPINPUT9_TRIPINPUT10_TRIPINPUT11_TRIPINPUT12_TRIPINPUT14_TRIPINPUT15_DCAHTRIPSEL_REG_DCALTRIPSEL_BITS_DCALTRIPSEL_REG_DCBCTL_BITS_DCBCTL_REG_DCBHTRIPSEL_BITS_DCBHTRIPSEL_REG_DCBLTRIPSEL_BITS_DCBLTRIPSEL_REG_DCCAPCTL_BITS_SHDWMODE_DCCAPCTL_REG_DCFCTL_BITS_BLANKINV_PULSESEL_DCFCTL_REG_DCSM_COMMON_REGS_SECTSTAT_DCSM_Z1_OTP_Z1OTP_LINKPOINTER1_Z1OTP_LINKPOINTER2_Z1OTP_LINKPOINTER3_Z1OTP_PSWDLOCK_Z1OTP_CRCLOCK_Z1OTP_BOOTCTRL_DCSM_Z1_REGS_Z1_LINKPOINTER_Z1_OTPSECLOCK_Z1_BOOTCTRL_Z1_LINKPOINTERERR_Z1_CSMKEY0_Z1_CSMKEY1_Z1_CSMKEY2_Z1_CSMKEY3_Z1_GRABSECTR_Z1_GRABRAMR_Z1_EXEONLYSECTR_Z1_EXEONLYRAMR_DCSM_Z2_OTP_Z2OTP_LINKPOINTER1_Z2OTP_LINKPOINTER2_Z2OTP_LINKPOINTER3_Z2OTP_PSWDLOCK_Z2OTP_CRCLOCK_Z2OTP_BOOTCTRL_DCSM_Z2_REGS_Z2_LINKPOINTER_Z2_OTPSECLOCK_Z2_BOOTCTRL_Z2_LINKPOINTERERR_Z2_CSMKEY0_Z2_CSMKEY1_Z2_CSMKEY2_Z2_CSMKEY3_Z2_GRABSECTR_Z2_GRABRAMR_Z2_EXEONLYSECTR_Z2_EXEONLYRAMR_DCTRIPSEL_BITS_DCAHCOMPSEL_DCALCOMPSEL_DCBHCOMPSEL_DCBLCOMPSEL_DCTRIPSEL_REG_DEBUGCTRL_BITS_DEBUGCTRL_REG_DEVCFGLOCK1_BITS_CPUSEL10_CPUSEL11_CPUSEL12_CPUSEL13_CPUSEL14_DEVCFGLOCK1_REG_DEV_CFG_REGS_DEVCFGLOCK1_SOFTPRES0_SOFTPRES1_SOFTPRES2_SOFTPRES3_SOFTPRES4_SOFTPRES5_SOFTPRES6_SOFTPRES7_SOFTPRES8_SOFTPRES9_SOFTPRES11_SOFTPRES13_SOFTPRES14_SOFTPRES16_CPU2RESCTL_DLYCTL_BITS_DLYCTL_REG_DMACHSRCSEL1_BITS_DMACHSRCSEL1_REG_DMACHSRCSEL2_BITS_DMACHSRCSEL2_REG_DMACHSRCSELLOCK_BITS_DMACHSRCSEL1_DMACHSRCSEL2_DMACHSRCSELLOCK_REG_DMACTRL_BITS_HARDRESET_PRIORITYRESET_DMACTRL_REG_DMA_CLA_SRC_SEL_REGS_CLA1TASKSRCSELLOCK_DMACHSRCSELLOCK_DMA_REGS_DEBUGCTRL_PRIORITYCTRL1_PRIORITYSTAT_DRR1_BITS_DRR1_REG_DRR2_BITS_DRR2_REG_DXR1_BITS_DXR1_REG_DXR2_BITS_DXR2_REG_DxACCPROT0_BITS_FETCHPROT_D0_CPUWRPROT_D0_FETCHPROT_D1_CPUWRPROT_D1_DxACCPROT0_REG_DxCOMMIT_BITS_COMMIT_D0_COMMIT_D1_DxCOMMIT_REG_DxINITDONE_BITS_INITDONE_M0_INITDONE_M1_INITDONE_D0_INITDONE_D1_DxINITDONE_REG_DxINIT_BITS_DxINIT_REG_DxLOCK_BITS_DxLOCK_REG_DxTEST_BITS_DxTEST_REG_ECAP_REGS_ECCLR_BITS_ECCLR_REG_ECCTL1_BITS_FREE_SOFT_ECCTL1_REG_ECCTL2_BITS_CONT_ONESHT_STOP_WRAP_TSCTRSTOP_SYNCI_EN_SYNCO_SEL_CAP_APWM_ECCTL2_REG_ECC_ENABLE_BITS_ECC_ENABLE_REG_ECEINT_BITS_CTR_EQ_PRD_CTR_EQ_CMP_ECEINT_REG_ECFLG_BITS_ECFLG_REG_ECFRC_BITS_ECFRC_REG_EMIF1ACCPROT0_BITS_FETCHPROT_EMIF1_CPUWRPROT_EMIF1_DMAWRPROT_EMIF1_EMIF1ACCPROT0_REG_EMIF1COMMIT_BITS_COMMIT_EMIF1_EMIF1COMMIT_REG_EMIF1LOCK_BITS_LOCK_EMIF1_EMIF1LOCK_REG_EMIF1MSEL_BITS_MSEL_EMIF1_EMIF1MSEL_REG_EMIF1_CONFIG_REGS_EMIF1LOCK_EMIF1COMMIT_EMIF1MSEL_EMIF1ACCPROT0_EMIF2ACCPROT0_BITS_EMIF2ACCPROT0_REG_EMIF2COMMIT_BITS_COMMIT_EMIF2_EMIF2COMMIT_REG_EMIF2LOCK_BITS_LOCK_EMIF2_EMIF2LOCK_REG_EMIF2_CONFIG_REGS_EMIF2LOCK_EMIF2COMMIT_EMIF2ACCPROT0_EMIF_REGS_ASYNC_WCCR_SDRAM_CR_SDRAM_RCR_ASYNC_CS2_CR_ASYNC_CS3_CR_ASYNC_CS4_CR_SDRAM_TR_TOTAL_SDRAM_AR_TOTAL_SDRAM_ACTR_SDR_EXT_TMNG_INT_MSK_SET_INT_MSK_CLR_ENINTST_BITS_ENINTST_REG_EPWMXLINK_BITS_TBPRDLINK_CMPALINK_CMPBLINK_CMPCLINK_CMPDLINK_GLDCTL2LINK_EPWMXLINK_REG_EPWM_REGS_AQTSRCSEL_EPWMXLINK_TZCTLDCA_TZCTLDCB_TZCBCFLG_TZOSTFLG_TZCBCCLR_TZOSTCLR_ETCNTINITCTL_ETCNTINIT_DCTRIPSEL_DCCAPCTL_DCFOFFSET_DCFOFFSETCNT_DCFWINDOW_DCFWINDOWCNT_DCAHTRIPSEL_DCALTRIPSEL_DCBHTRIPSEL_DCBLTRIPSEL_EPWM_XBAR_REGS_TRIP4MUX0TO15CFG_TRIP4MUX16TO31CFG_TRIP5MUX0TO15CFG_TRIP5MUX16TO31CFG_TRIP7MUX0TO15CFG_TRIP7MUX16TO31CFG_TRIP8MUX0TO15CFG_TRIP8MUX16TO31CFG_TRIP9MUX0TO15CFG_TRIP9MUX16TO31CFG_TRIP10MUX0TO15CFG_TRIP10MUX16TO31CFG_TRIP11MUX0TO15CFG_TRIP11MUX16TO31CFG_TRIP12MUX0TO15CFG_TRIP12MUX16TO31CFG_TRIP4MUXENABLE_TRIP5MUXENABLE_TRIP7MUXENABLE_TRIP8MUXENABLE_TRIP9MUXENABLE_TRIP10MUXENABLE_TRIP11MUXENABLE_TRIP12MUXENABLE_TRIPOUTINV_TRIPLOCK_EQEP_REGS_QPOSINIT_QPOSILAT_QPOSSLAT_QCTMRLAT_QCPRDLAT_ERR_CNT_BITS_ERR_CNT_REG_ERR_INTCLR_BITS_SINGLE_ERR_INTCLR_UNC_ERR_INTCLR_ERR_INTCLR_REG_ERR_INTFLG_BITS_SINGLE_ERR_INTFLG_UNC_ERR_INTFLG_ERR_INTFLG_REG_ERR_POS_BITS_ERR_POS_L_ERR_TYPE_L_ERR_POS_H_ERR_TYPE_H_ERR_POS_REG_ERR_STATUS_BITS_FAIL_0_L_FAIL_1_L_UNC_ERR_L_FAIL_0_H_FAIL_1_H_UNC_ERR_H_ERR_STATUS_CLR_BITS_FAIL_0_L_CLR_FAIL_1_L_CLR_UNC_ERR_L_CLR_FAIL_0_H_CLR_FAIL_1_H_CLR_UNC_ERR_H_CLR_ERR_STATUS_CLR_REG_ERR_STATUS_REG_ERR_THRESHOLD_BITS_ERR_THRESHOLD_ERR_THRESHOLD_REG_ETCLR_BITS_ETCLR_REG_ETCNTINITCTL_BITS_INTINITFRC_SOCAINITFRC_SOCBINITFRC_INTINITEN_SOCAINITEN_SOCBINITEN_ETCNTINITCTL_REG_ETCNTINIT_BITS_SOCAINIT_SOCBINIT_ETCNTINIT_REG_ETFLG_BITS_ETFLG_REG_ETFRC_BITS_ETFRC_REG_ETINTPS_BITS_ETINTPS_REG_ETPS_BITS_INTPSSEL_SOCPSSEL_ETPS_REG_ETSEL_BITS_SOCASELCMP_SOCBSELCMP_INTSELCMP_ETSEL_REG_ETSOCPS_BITS_SOCAPRD2_SOCACNT2_SOCBPRD2_SOCBCNT2_ETSOCPS_REG_EXTADCSOCSELECT_BITS_PWM1SOCAEN_PWM2SOCAEN_PWM3SOCAEN_PWM4SOCAEN_PWM5SOCAEN_PWM6SOCAEN_PWM7SOCAEN_PWM8SOCAEN_PWM9SOCAEN_PWM10SOCAEN_PWM11SOCAEN_PWM12SOCAEN_PWM1SOCBEN_PWM2SOCBEN_PWM3SOCBEN_PWM4SOCBEN_PWM5SOCBEN_PWM6SOCBEN_PWM7SOCBEN_PWM8SOCBEN_PWM9SOCBEN_PWM10SOCBEN_PWM11SOCBEN_PWM12SOCBEN_EXTADCSOCSELECT_REG_FADDR_TEST_BITS_FADDR_TEST_REG_FBAC_BITS_FBAC_REG_FBFALLBACK_BITS_FBFALLBACK_REG_FBPRDY_BITS_FBPRDY_REG_FECC_CTRL_BITS_ECC_TEST_EN_ECC_SELECT_DO_ECC_CALC_FECC_CTRL_REG_FECC_STATUS_BITS_SINGLE_ERR_DATA_ERR_POS_ERR_TYPE_FECC_STATUS_REG_FECC_TEST_BITS_FECC_TEST_REG_FLASH_CTRL_REGS_FBFALLBACK_FRD_INTF_CTRL_FLASH_ECC_REGS_ECC_ENABLE_SINGLE_ERR_ADDR_LOW_SINGLE_ERR_ADDR_HIGH_UNC_ERR_ADDR_LOW_UNC_ERR_ADDR_HIGH_ERR_STATUS_ERR_STATUS_CLR_ERR_INTFLG_ERR_INTCLR_FDATAH_TEST_FDATAL_TEST_FADDR_TEST_FECC_TEST_FECC_CTRL_FOUTH_TEST_FOUTL_TEST_FECC_STATUS_FLSEM_BITS_FLSEM_REG_FMAC_BITS_FMAC_REG_FMSTAT_BITS_VOLTSTAT_FMSTAT_REG_FPAC1_BITS_FPAC1_REG_FPAC2_BITS_FPAC2_REG_FRDCNTL_BITS_FRDCNTL_REG_FRD_INTF_CTRL_BITS_PREFETCH_EN_DATA_CACHE_EN_FRD_INTF_CTRL_REG_FSPRD_BITS_FSPRD_REG_FUSEERR_BITS_FUSEERR_REG_GINTCLR_BITS_GINTCLR_REG_GINTEN_BITS_GINTEN_REG_GINTFLG_BITS_GINTFLG_REG_GLDCFG_BITS_TBPRD_TBPRDHR_CMPA_CMPAHR_CMPB_CMPBHR_DBRED_DBREDHR_DBFED_DBFEDHR_AQCTLA_AQCTLA2_AQCTLB_AQCTLB2_GLDCFG_REG_GLDCTL2_BITS_GLDCTL2_REG_GLDCTL_BITS_OSHTMODE_GLDCTL_REG_GPACLEAR_BITS_GPACLEAR_REG_GPACR_BITS_GPACR_REG_GPACSEL1_BITS_GPACSEL1_REG_GPACSEL2_BITS_GPACSEL2_REG_GPACSEL3_BITS_GPACSEL3_REG_GPACSEL4_BITS_GPACSEL4_REG_GPACTRL_BITS_QUALPRD0_QUALPRD1_QUALPRD2_QUALPRD3_GPACTRL_REG_GPADAT_BITS_GPADAT_REG_GPADIR_BITS_GPADIR_REG_GPAGMUX1_BITS_GPAGMUX1_REG_GPAGMUX2_BITS_GPAGMUX2_REG_GPAINV_BITS_GPAINV_REG_GPALOCK_BITS_GPALOCK_REG_GPAMUX1_BITS_GPAMUX1_REG_GPAMUX2_BITS_GPAMUX2_REG_GPAODR_BITS_GPAODR_REG_GPAPUD_BITS_GPAPUD_REG_GPAQSEL1_BITS_GPAQSEL1_REG_GPAQSEL2_BITS_GPAQSEL2_REG_GPASET_BITS_GPASET_REG_GPATOGGLE_BITS_GPATOGGLE_REG_GPBAMSEL_BITS_GPBAMSEL_REG_GPBCLEAR_BITS_GPBCLEAR_REG_GPBCR_BITS_GPBCR_REG_GPBCSEL1_BITS_GPBCSEL1_REG_GPBCSEL2_BITS_GPBCSEL2_REG_GPBCSEL3_BITS_GPBCSEL3_REG_GPBCSEL4_BITS_GPBCSEL4_REG_GPBCTRL_BITS_GPBCTRL_REG_GPBDAT_BITS_GPBDAT_REG_GPBDIR_BITS_GPBDIR_REG_GPBGMUX1_BITS_GPBGMUX1_REG_GPBGMUX2_BITS_GPBGMUX2_REG_GPBINV_BITS_GPBINV_REG_GPBLOCK_BITS_GPBLOCK_REG_GPBMUX1_BITS_GPBMUX1_REG_GPBMUX2_BITS_GPBMUX2_REG_GPBODR_BITS_GPBODR_REG_GPBPUD_BITS_GPBPUD_REG_GPBQSEL1_BITS_GPBQSEL1_REG_GPBQSEL2_BITS_GPBQSEL2_REG_GPBSET_BITS_GPBSET_REG_GPBTOGGLE_BITS_GPBTOGGLE_REG_GPCCLEAR_BITS_GPCCLEAR_REG_GPCCR_BITS_GPCCR_REG_GPCCSEL1_BITS_GPCCSEL1_REG_GPCCSEL2_BITS_GPCCSEL2_REG_GPCCSEL3_BITS_GPCCSEL3_REG_GPCCSEL4_BITS_GPCCSEL4_REG_GPCCTRL_BITS_GPCCTRL_REG_GPCDAT_BITS_GPCDAT_REG_GPCDIR_BITS_GPCDIR_REG_GPCGMUX1_BITS_GPCGMUX1_REG_GPCGMUX2_BITS_GPCGMUX2_REG_GPCINV_BITS_GPCINV_REG_GPCLOCK_BITS_GPCLOCK_REG_GPCMUX1_BITS_GPCMUX1_REG_GPCMUX2_BITS_GPCMUX2_REG_GPCODR_BITS_GPCODR_REG_GPCPUD_BITS_GPCPUD_REG_GPCQSEL1_BITS_GPCQSEL1_REG_GPCQSEL2_BITS_GPCQSEL2_REG_GPCSET_BITS_GPCSET_REG_GPCTOGGLE_BITS_GPCTOGGLE_REG_GPDCLEAR_BITS_GPDCLEAR_REG_GPDCR_BITS_GPDCR_REG_GPDCSEL1_BITS_GPDCSEL1_REG_GPDCSEL2_BITS_GPDCSEL2_REG_GPDCSEL3_BITS_GPDCSEL3_REG_GPDCSEL4_BITS_GPDCSEL4_REG_GPDCTRL_BITS_GPDCTRL_REG_GPDDAT_BITS_GPDDAT_REG_GPDDIR_BITS_GPDDIR_REG_GPDGMUX1_BITS_GPDGMUX1_REG_GPDGMUX2_BITS_GPDGMUX2_REG_GPDINV_BITS_GPDINV_REG_GPDLOCK_BITS_GPDLOCK_REG_GPDMUX1_BITS_GPDMUX1_REG_GPDMUX2_BITS_GPDMUX2_REG_GPDODR_BITS_GPDODR_REG_GPDPUD_BITS_GPDPUD_REG_GPDQSEL1_BITS_GPDQSEL1_REG_GPDQSEL2_BITS_GPDQSEL2_REG_GPDSET_BITS_GPDSET_REG_GPDTOGGLE_BITS_GPDTOGGLE_REG_GPECLEAR_BITS_GPECLEAR_REG_GPECR_BITS_GPECR_REG_GPECSEL1_BITS_GPECSEL1_REG_GPECSEL2_BITS_GPECSEL2_REG_GPECSEL3_BITS_GPECSEL3_REG_GPECSEL4_BITS_GPECSEL4_REG_GPECTRL_BITS_GPECTRL_REG_GPEDAT_BITS_GPEDAT_REG_GPEDIR_BITS_GPEDIR_REG_GPEGMUX1_BITS_GPEGMUX1_REG_GPEGMUX2_BITS_GPEGMUX2_REG_GPEINV_BITS_GPEINV_REG_GPELOCK_BITS_GPELOCK_REG_GPEMUX1_BITS_GPEMUX1_REG_GPEMUX2_BITS_GPEMUX2_REG_GPEODR_BITS_GPEODR_REG_GPEPUD_BITS_GPEPUD_REG_GPEQSEL1_BITS_GPEQSEL1_REG_GPEQSEL2_BITS_GPEQSEL2_REG_GPESET_BITS_GPESET_REG_GPETOGGLE_BITS_GPETOGGLE_REG_GPFCLEAR_BITS_GPFCLEAR_REG_GPFCR_BITS_GPFCR_REG_GPFCSEL1_BITS_GPFCSEL1_REG_GPFCSEL2_BITS_GPFCSEL2_REG_GPFCTRL_BITS_GPFCTRL_REG_GPFDAT_BITS_GPFDAT_REG_GPFDIR_BITS_GPFDIR_REG_GPFGMUX1_BITS_GPFGMUX1_REG_GPFINV_BITS_GPFINV_REG_GPFLOCK_BITS_GPFLOCK_REG_GPFMUX1_BITS_GPFMUX1_REG_GPFODR_BITS_GPFODR_REG_GPFPUD_BITS_GPFPUD_REG_GPFQSEL1_BITS_GPFQSEL1_REG_GPFSET_BITS_GPFSET_REG_GPFTOGGLE_BITS_GPFTOGGLE_REG_GPIOLPMSEL0_BITS_GPIOLPMSEL0_REG_GPIOLPMSEL1_BITS_GPIOLPMSEL1_REG_GPIO_CTRL_REGS_GPAQSEL1_GPAQSEL2_GPAGMUX1_GPAGMUX2_GPACSEL1_GPACSEL2_GPACSEL3_GPACSEL4_GPBQSEL1_GPBQSEL2_GPBAMSEL_GPBGMUX1_GPBGMUX2_GPBCSEL1_GPBCSEL2_GPBCSEL3_GPBCSEL4_GPCQSEL1_GPCQSEL2_GPCGMUX1_GPCGMUX2_GPCCSEL1_GPCCSEL2_GPCCSEL3_GPCCSEL4_GPDQSEL1_GPDQSEL2_GPDGMUX1_GPDGMUX2_GPDCSEL1_GPDCSEL2_GPDCSEL3_GPDCSEL4_GPEQSEL1_GPEQSEL2_GPEGMUX1_GPEGMUX2_GPECSEL1_GPECSEL2_GPECSEL3_GPECSEL4_GPFQSEL1_GPFGMUX1_GPFCSEL1_GPFCSEL2_GPIO_DATA_REGS_GPACLEAR_GPATOGGLE_GPBCLEAR_GPBTOGGLE_GPCCLEAR_GPCTOGGLE_GPDCLEAR_GPDTOGGLE_GPECLEAR_GPETOGGLE_GPFCLEAR_GPFTOGGLE_GSxACCPROT0_BITS_FETCHPROT_GS0_CPUWRPROT_GS0_DMAWRPROT_GS0_FETCHPROT_GS1_CPUWRPROT_GS1_DMAWRPROT_GS1_FETCHPROT_GS2_CPUWRPROT_GS2_DMAWRPROT_GS2_FETCHPROT_GS3_CPUWRPROT_GS3_DMAWRPROT_GS3_GSxACCPROT0_REG_GSxACCPROT1_BITS_FETCHPROT_GS4_CPUWRPROT_GS4_DMAWRPROT_GS4_FETCHPROT_GS5_CPUWRPROT_GS5_DMAWRPROT_GS5_FETCHPROT_GS6_CPUWRPROT_GS6_DMAWRPROT_GS6_FETCHPROT_GS7_CPUWRPROT_GS7_DMAWRPROT_GS7_GSxACCPROT1_REG_GSxACCPROT2_BITS_FETCHPROT_GS8_CPUWRPROT_GS8_DMAWRPROT_GS8_FETCHPROT_GS9_CPUWRPROT_GS9_DMAWRPROT_GS9_FETCHPROT_GS10_CPUWRPROT_GS10_DMAWRPROT_GS10_FETCHPROT_GS11_CPUWRPROT_GS11_DMAWRPROT_GS11_GSxACCPROT2_REG_GSxACCPROT3_BITS_FETCHPROT_GS12_CPUWRPROT_GS12_DMAWRPROT_GS12_FETCHPROT_GS13_CPUWRPROT_GS13_DMAWRPROT_GS13_FETCHPROT_GS14_CPUWRPROT_GS14_DMAWRPROT_GS14_FETCHPROT_GS15_CPUWRPROT_GS15_DMAWRPROT_GS15_GSxACCPROT3_REG_GSxCOMMIT_BITS_COMMIT_GS0_COMMIT_GS1_COMMIT_GS2_COMMIT_GS3_COMMIT_GS4_COMMIT_GS5_COMMIT_GS6_COMMIT_GS7_COMMIT_GS8_COMMIT_GS9_COMMIT_GS10_COMMIT_GS11_COMMIT_GS12_COMMIT_GS13_COMMIT_GS14_COMMIT_GS15_GSxCOMMIT_REG_GSxINITDONE_BITS_INITDONE_GS0_INITDONE_GS1_INITDONE_GS2_INITDONE_GS3_INITDONE_GS4_INITDONE_GS5_INITDONE_GS6_INITDONE_GS7_INITDONE_GS8_INITDONE_GS9_INITDONE_GS10_INITDONE_GS11_INITDONE_GS12_INITDONE_GS13_INITDONE_GS14_INITDONE_GS15_GSxINITDONE_REG_GSxINIT_BITS_INIT_GS0_INIT_GS1_INIT_GS2_INIT_GS3_INIT_GS4_INIT_GS5_INIT_GS6_INIT_GS7_INIT_GS8_INIT_GS9_INIT_GS10_INIT_GS11_INIT_GS12_INIT_GS13_INIT_GS14_INIT_GS15_GSxINIT_REG_GSxLOCK_BITS_LOCK_GS0_LOCK_GS1_LOCK_GS2_LOCK_GS3_LOCK_GS4_LOCK_GS5_LOCK_GS6_LOCK_GS7_LOCK_GS8_LOCK_GS9_LOCK_GS10_LOCK_GS11_LOCK_GS12_LOCK_GS13_LOCK_GS14_LOCK_GS15_GSxLOCK_REG_GSxMSEL_BITS_MSEL_GS0_MSEL_GS1_MSEL_GS2_MSEL_GS3_MSEL_GS4_MSEL_GS5_MSEL_GS6_MSEL_GS7_MSEL_GS8_MSEL_GS9_MSEL_GS10_MSEL_GS11_MSEL_GS12_MSEL_GS13_MSEL_GS14_MSEL_GS15_GSxMSEL_REG_GSxTEST_BITS_TEST_GS0_TEST_GS1_TEST_GS2_TEST_GS3_TEST_GS4_TEST_GS5_TEST_GS6_TEST_GS7_TEST_GS8_TEST_GS9_TEST_GS10_TEST_GS11_TEST_GS12_TEST_GS13_TEST_GS14_TEST_GS15_GSxTEST_REG_HRCNFG_BITS_AUTOCONV_EDGMODEB_CTLMODEB_HRCNFG_REG_HRMSTEP_BITS_HRMSTEP_REG_HRPCTL_BITS_TBPHSHRLOADE_PWMSYNCSELX_HRPCTL_REG_HRPWR_BITS_CALPWRON_HRPWR_REG_I2CDRR_BITS_I2CDRR_REG_I2CDXR_BITS_I2CDXR_REG_I2CEMDR_BITS_I2CEMDR_REG_I2CFFRX_BITS_RXFFIENA_RXFFINTCLR_I2CFFRX_REG_I2CFFTX_BITS_TXFFIENA_TXFFINTCLR_I2CFFTX_REG_I2CIER_BITS_I2CIER_REG_I2CISRC_BITS_I2CISRC_REG_I2CMDR_BITS_I2CMDR_REG_I2COAR_BITS_I2COAR_REG_I2CPSC_BITS_I2CPSC_REG_I2CSAR_BITS_I2CSAR_REG_I2CSTR_BITS_I2CSTR_REG_I2C_REGS_IFCFG_BITS_STARTPOLA_WAITPOLA_IFCFG_REG_IFIVAL_BITS_IFIVAL_REG_INPUTSELECTLOCK_BITS_INPUT1SELECT_INPUT2SELECT_INPUT3SELECT_INPUT4SELECT_INPUT5SELECT_INPUT6SELECT_INPUT7SELECT_INPUT8SELECT_INPUT9SELECT_INPUT10SELECT_INPUT11SELECT_INPUT12SELECT_INPUT13SELECT_INPUT14SELECT_INPUT15SELECT_INPUT16SELECT_INPUTSELECTLOCK_REG_INPUT_XBAR_REGS_INPUTSELECTLOCK_INTENCLR_BITS_INTENCLR_REG_INTENSET_BITS_INTENSET_REG_INTOSC1TRIM_BITS_VALFINETRIM_INTOSC1TRIM_REG_INTOSC2TRIM_BITS_INTOSC2TRIM_REG_INT_MSK_BITS_AT_MASKED_LT_MASKED_WR_MASKED_INT_MSK_CLR_BITS_AT_MASK_CLR_LT_MASK_CLR_WR_MASK_CLR_INT_MSK_CLR_REG_INT_MSK_REG_INT_MSK_SET_BITS_AT_MASK_SET_LT_MASK_SET_WR_MASK_SET_INT_MSK_SET_REG_INT_RAW_BITS_INT_RAW_REG_IORESTOREADDR_BITS_IORESTOREADDR_REG_IPCACK_BITS_IPCACK_REG_IPCCLR_BITS_IPCCLR_REG_IPCFLG_BITS_IPCFLG_REG_IPCSET_BITS_IPCSET_REG_IPCSTS_BITS_IPCSTS_REG_IPC_REGS_CPU1_IPCCOUNTERL_IPCCOUNTERH_IPCSENDCOM_IPCSENDADDR_IPCSENDDATA_IPCREMOTEREPLY_IPCRECVCOM_IPCRECVADDR_IPCRECVDATA_IPCLOCALREPLY_IPCBOOTSTS_IPCBOOTMODE_PUMPREQUEST_LOCK_BITS_LOCK_REG_LOSPCP_BITS_LSPCLKDIV_LOSPCP_REG_LPMCR_BITS_QUALSTDBY_M0M1MODE_IOISODIS_LPMCR_REG_LPMSTAT_BITS_CPU2LPMSTAT_LPMSTAT_REG_LSxACCPROT0_BITS_FETCHPROT_LS0_CPUWRPROT_LS0_FETCHPROT_LS1_CPUWRPROT_LS1_FETCHPROT_LS2_CPUWRPROT_LS2_FETCHPROT_LS3_CPUWRPROT_LS3_LSxACCPROT0_REG_LSxACCPROT1_BITS_FETCHPROT_LS4_CPUWRPROT_LS4_FETCHPROT_LS5_CPUWRPROT_LS5_LSxACCPROT1_REG_LSxCLAPGM_BITS_CLAPGM_LS0_CLAPGM_LS1_CLAPGM_LS2_CLAPGM_LS3_CLAPGM_LS4_CLAPGM_LS5_LSxCLAPGM_REG_LSxCOMMIT_BITS_COMMIT_LS0_COMMIT_LS1_COMMIT_LS2_COMMIT_LS3_COMMIT_LS4_COMMIT_LS5_LSxCOMMIT_REG_LSxINITDONE_BITS_INITDONE_LS0_INITDONE_LS1_INITDONE_LS2_INITDONE_LS3_INITDONE_LS4_INITDONE_LS5_LSxINITDONE_REG_LSxINIT_BITS_INIT_LS0_INIT_LS1_INIT_LS2_INIT_LS3_INIT_LS4_INIT_LS5_LSxINIT_REG_LSxLOCK_BITS_LOCK_LS0_LOCK_LS1_LOCK_LS2_LOCK_LS3_LOCK_LS4_LOCK_LS5_LSxLOCK_REG_LSxMSEL_BITS_MSEL_LS0_MSEL_LS1_MSEL_LS2_MSEL_LS3_MSEL_LS4_MSEL_LS5_LSxMSEL_REG_LSxTEST_BITS_TEST_LS0_TEST_LS1_TEST_LS2_TEST_LS3_TEST_LS4_TEST_LS5_LSxTEST_REG_MAVCLR_BITS_CPUFETCH_CPUWRITE_DMAWRITE_MAVCLR_REG_MAVFLG_BITS_MAVFLG_REG_MAVINTEN_BITS_MAVINTEN_REG_MAVSET_BITS_MAVSET_REG_MCDCR_BITS_MCDCR_REG_MCR1_BITS_MCR1_REG_MCR2_BITS_MCR2_REG_MCTL_BITS_MCTL_REG_MEMORY_ERROR_REGS_UCERRFLG_UCERRSET_UCERRCLR_UCCPUREADDR_UCDMAREADDR_UCCLA1READDR_CCPUREADDR_CERRTHRES_CEINTFLG_MEM_CFG_REGS_DxCOMMIT_DxACCPROT0_DxINITDONE_LSxCOMMIT_LSxCLAPGM_LSxACCPROT0_LSxACCPROT1_LSxINITDONE_GSxCOMMIT_GSxACCPROT0_GSxACCPROT1_GSxACCPROT2_GSxACCPROT3_GSxINITDONE_MSGxTEST_MSGxINIT_MSGxINITDONE_MFFINT_BITS_MFFINT_REG_MICLROVF_BITS_MICLROVF_REG_MICLR_BITS_MICLR_REG_MIER_BITS_MIER_REG_MIFRC_BITS_MIFRC_REG_MIFR_BITS_MIFR_REG_MIOVF_BITS_MIOVF_REG_MIRUN_BITS_MIRUN_REG_MODE_BITS_PERINTSEL_CHINTMODE_CONTINUOUS_DATASIZE_MODE_REG_MSGxINITDONE_BITS_INITDONE_CPUTOCPU_INITDONE_CPUTOCLA1_INITDONE_CLA1TOCPU_MSGxINITDONE_REG_MSGxINIT_BITS_INIT_CPUTOCPU_INIT_CPUTOCLA1_INIT_CLA1TOCPU_MSGxINIT_REG_MSGxTEST_BITS_TEST_CPUTOCPU_TEST_CPUTOCLA1_TEST_CLA1TOCPU_MSGxTEST_REG_McBSP_REGS_NMAVCLR_BITS_CLA1READ_CLA1WRITE_CLA1FETCH_NMAVCLR_REG_NMAVFLG_BITS_NMAVFLG_REG_NMAVINTEN_BITS_NMAVINTEN_REG_NMAVSET_BITS_NMAVSET_REG_NMICFG_BITS_NMICFG_REG_NMIFLGCLR_BITS_CLOCKFAIL_RAMUNCERR_FLUNCERR_CPU1HWBISTERR_CPU2HWBISTERR_PIEVECTERR_CPU2WDRSn_CPU2NMIWDRSn_NMIFLGCLR_REG_NMIFLGFRC_BITS_NMIFLGFRC_REG_NMIFLG_BITS_NMIFLG_REG_NMISHDFLG_BITS_NMISHDFLG_REG_NMI_INTRUPT_REGS_NMIFLGCLR_NMIFLGFRC_NMIWDCNT_NMIWDPRD_NMISHDFLG_OUTPUT1MUX0TO15CFG_BITS_OUTPUT1MUX0TO15CFG_REG_OUTPUT1MUX16TO31CFG_BITS_OUTPUT1MUX16TO31CFG_REG_OUTPUT1MUXENABLE_BITS_OUTPUT1MUXENABLE_REG_OUTPUT2MUX0TO15CFG_BITS_OUTPUT2MUX0TO15CFG_REG_OUTPUT2MUX16TO31CFG_BITS_OUTPUT2MUX16TO31CFG_REG_OUTPUT2MUXENABLE_BITS_OUTPUT2MUXENABLE_REG_OUTPUT3MUX0TO15CFG_BITS_OUTPUT3MUX0TO15CFG_REG_OUTPUT3MUX16TO31CFG_BITS_OUTPUT3MUX16TO31CFG_REG_OUTPUT3MUXENABLE_BITS_OUTPUT3MUXENABLE_REG_OUTPUT4MUX0TO15CFG_BITS_OUTPUT4MUX0TO15CFG_REG_OUTPUT4MUX16TO31CFG_BITS_OUTPUT4MUX16TO31CFG_REG_OUTPUT4MUXENABLE_BITS_OUTPUT4MUXENABLE_REG_OUTPUT5MUX0TO15CFG_BITS_OUTPUT5MUX0TO15CFG_REG_OUTPUT5MUX16TO31CFG_BITS_OUTPUT5MUX16TO31CFG_REG_OUTPUT5MUXENABLE_BITS_OUTPUT5MUXENABLE_REG_OUTPUT6MUX0TO15CFG_BITS_OUTPUT6MUX0TO15CFG_REG_OUTPUT6MUX16TO31CFG_BITS_OUTPUT6MUX16TO31CFG_REG_OUTPUT6MUXENABLE_BITS_OUTPUT6MUXENABLE_REG_OUTPUT7MUX0TO15CFG_BITS_OUTPUT7MUX0TO15CFG_REG_OUTPUT7MUX16TO31CFG_BITS_OUTPUT7MUX16TO31CFG_REG_OUTPUT7MUXENABLE_BITS_OUTPUT7MUXENABLE_REG_OUTPUT8MUX0TO15CFG_BITS_OUTPUT8MUX0TO15CFG_REG_OUTPUT8MUX16TO31CFG_BITS_OUTPUT8MUX16TO31CFG_REG_OUTPUT8MUXENABLE_BITS_OUTPUT8MUXENABLE_REG_OUTPUTINV_BITS_OUTPUTINV_REG_OUTPUTLATCHCLR_BITS_OUTPUTLATCHCLR_REG_OUTPUTLATCHENABLE_BITS_OUTPUTLATCHENABLE_REG_OUTPUTLATCHFRC_BITS_OUTPUTLATCHFRC_REG_OUTPUTLATCH_BITS_OUTPUTLATCH_REG_OUTPUTLOCK_BITS_OUTPUTLOCK_REG_OUTPUT_XBAR_REGS_OUTPUT1MUX0TO15CFG_OUTPUT1MUX16TO31CFG_OUTPUT2MUX0TO15CFG_OUTPUT2MUX16TO31CFG_OUTPUT3MUX0TO15CFG_OUTPUT3MUX16TO31CFG_OUTPUT4MUX0TO15CFG_OUTPUT4MUX16TO31CFG_OUTPUT5MUX0TO15CFG_OUTPUT5MUX16TO31CFG_OUTPUT6MUX0TO15CFG_OUTPUT6MUX16TO31CFG_OUTPUT7MUX0TO15CFG_OUTPUT7MUX16TO31CFG_OUTPUT8MUX0TO15CFG_OUTPUT8MUX16TO31CFG_OUTPUT1MUXENABLE_OUTPUT2MUXENABLE_OUTPUT3MUXENABLE_OUTPUT4MUXENABLE_OUTPUT5MUXENABLE_OUTPUT6MUXENABLE_OUTPUT7MUXENABLE_OUTPUT8MUXENABLE_OUTPUTLATCH_OUTPUTLATCHCLR_OUTPUTLATCHFRC_OUTPUTLATCHENABLE_OUTPUTINV_OUTPUTLOCK_PARTIDH_BITS_DEVICE_CLASS_ID_PARTIDH_REG_PARTIDL_BITS_PIN_COUNT_INSTASPIN_FLASH_SIZE_PARTID_FORMAT_REVISION_PARTIDL_REG_PCCTL_BITS_PCCTL_REG_PCLKCR0_BITS_CPUTIMER0_CPUTIMER1_CPUTIMER2_TBCLKSYNC_GTBCLKSYNC_PCLKCR0_REG_PCLKCR10_BITS_PCLKCR10_REG_PCLKCR11_BITS_PCLKCR11_REG_PCLKCR12_BITS_PCLKCR12_REG_PCLKCR13_BITS_PCLKCR13_REG_PCLKCR14_BITS_PCLKCR14_REG_PCLKCR16_BITS_PCLKCR16_REG_PCLKCR1_BITS_PCLKCR1_REG_PCLKCR2_BITS_PCLKCR2_REG_PCLKCR3_BITS_PCLKCR3_REG_PCLKCR4_BITS_PCLKCR4_REG_PCLKCR6_BITS_PCLKCR6_REG_PCLKCR7_BITS_PCLKCR7_REG_PCLKCR8_BITS_PCLKCR8_REG_PCLKCR9_BITS_PCLKCR9_REG_PCR_BITS_PERCLKDIVSEL_BITS_EPWMCLKDIV_EMIF1CLKDIV_EMIF2CLKDIV_PERCLKDIVSEL_REG_PERCNF1_BITS_ADC_A_MODE_ADC_B_MODE_ADC_C_MODE_ADC_D_MODE_USB_A_PHY_PERCNF1_REG_PERCTL_BITS_PERCTL_REG_PIEACK_BITS_PIEACK_REG_PIECTRL_BITS_PIECTRL_REG_PIEIER10_BITS_PIEIER10_REG_PIEIER11_BITS_PIEIER11_REG_PIEIER12_BITS_PIEIER12_REG_PIEIER1_BITS_PIEIER1_REG_PIEIER2_BITS_PIEIER2_REG_PIEIER3_BITS_PIEIER3_REG_PIEIER4_BITS_PIEIER4_REG_PIEIER5_BITS_PIEIER5_REG_PIEIER6_BITS_PIEIER6_REG_PIEIER7_BITS_PIEIER7_REG_PIEIER8_BITS_PIEIER8_REG_PIEIER9_BITS_PIEIER9_REG_PIEIFR10_BITS_PIEIFR10_REG_PIEIFR11_BITS_PIEIFR11_REG_PIEIFR12_BITS_PIEIFR12_REG_PIEIFR1_BITS_PIEIFR1_REG_PIEIFR2_BITS_PIEIFR2_REG_PIEIFR3_BITS_PIEIFR3_REG_PIEIFR4_BITS_PIEIFR4_REG_PIEIFR5_BITS_PIEIFR5_REG_PIEIFR6_BITS_PIEIFR6_REG_PIEIFR7_BITS_PIEIFR7_REG_PIEIFR8_BITS_PIEIFR8_REG_PIEIFR9_BITS_PIEIFR9_REG_PIEVERRADDR_BITS_PIEVERRADDR_REG_PIE_CTRL_REGS_PIEIER10_PIEIFR10_PIEIER11_PIEIFR11_PIEIER12_PIEIFR12_PIE_VECT_TABLE_PIE1_RESERVED_INT_PIE2_RESERVED_INT_PIE3_RESERVED_INT_PIE4_RESERVED_INT_PIE5_RESERVED_INT_PIE6_RESERVED_INT_PIE7_RESERVED_INT_PIE8_RESERVED_INT_PIE9_RESERVED_INT_PIE10_RESERVED_INT_PIE11_RESERVED_INT_PIE12_RESERVED_INT_PIE13_RESERVED_INT_TIMER1_INT_TIMER2_INT_DATALOG_INT_RTOS_INT_ILLEGAL_INT_USER1_INT_USER2_INT_USER3_INT_USER4_INT_USER5_INT_USER6_INT_USER7_INT_USER8_INT_USER9_INT_USER10_INT_USER11_INT_USER12_INT_ADCA1_INT_ADCB1_INT_ADCC1_INT_XINT1_INT_XINT2_INT_ADCD1_INT_TIMER0_INT_WAKE_INT_EPWM1_TZ_INT_EPWM2_TZ_INT_EPWM3_TZ_INT_EPWM4_TZ_INT_EPWM5_TZ_INT_EPWM6_TZ_INT_EPWM7_TZ_INT_EPWM8_TZ_INT_EPWM1_INT_EPWM2_INT_EPWM3_INT_EPWM4_INT_EPWM5_INT_EPWM6_INT_EPWM7_INT_EPWM8_INT_ECAP1_INT_ECAP2_INT_ECAP3_INT_ECAP4_INT_ECAP5_INT_ECAP6_INT_PIE14_RESERVED_INT_PIE15_RESERVED_INT_EQEP1_INT_EQEP2_INT_EQEP3_INT_PIE16_RESERVED_INT_PIE17_RESERVED_INT_PIE18_RESERVED_INT_PIE19_RESERVED_INT_PIE20_RESERVED_INT_SPIA_RX_INT_SPIA_TX_INT_SPIB_RX_INT_SPIB_TX_INT_MCBSPA_RX_INT_MCBSPA_TX_INT_MCBSPB_RX_INT_MCBSPB_TX_INT_DMA_CH1_INT_DMA_CH2_INT_DMA_CH3_INT_DMA_CH4_INT_DMA_CH5_INT_DMA_CH6_INT_PIE21_RESERVED_INT_PIE22_RESERVED_INT_I2CA_INT_I2CA_FIFO_INT_I2CB_INT_I2CB_FIFO_INT_SCIC_RX_INT_SCIC_TX_INT_SCID_RX_INT_SCID_TX_INT_SCIA_RX_INT_SCIA_TX_INT_SCIB_RX_INT_SCIB_TX_INT_DCANA_1_INT_DCANA_2_INT_DCANB_1_INT_DCANB_2_INT_ADCA_EVT_INT_ADCA2_INT_ADCA3_INT_ADCA4_INT_ADCB_EVT_INT_ADCB2_INT_ADCB3_INT_ADCB4_INT_CLA1_1_INT_CLA1_2_INT_CLA1_3_INT_CLA1_4_INT_CLA1_5_INT_CLA1_6_INT_CLA1_7_INT_CLA1_8_INT_XINT3_INT_XINT4_INT_XINT5_INT_PBIST_INT_PIE23_RESERVED_INT_FPU_OVERFLOW_INT_FPU_UNDERFLOW_INT_PIE24_RESERVED_INT_PIE25_RESERVED_INT_PIE26_RESERVED_INT_PIE27_RESERVED_INT_IPC0_INT_IPC1_INT_IPC2_INT_IPC3_INT_EPWM9_TZ_INT_EPWM10_TZ_INT_EPWM11_TZ_INT_EPWM12_TZ_INT_PIE28_RESERVED_INT_PIE29_RESERVED_INT_PIE30_RESERVED_INT_PIE31_RESERVED_INT_EPWM9_INT_EPWM10_INT_EPWM11_INT_EPWM12_INT_PIE32_RESERVED_INT_PIE33_RESERVED_INT_PIE34_RESERVED_INT_PIE35_RESERVED_INT_PIE36_RESERVED_INT_PIE37_RESERVED_INT_PIE38_RESERVED_INT_PIE39_RESERVED_INT_PIE40_RESERVED_INT_PIE41_RESERVED_INT_PIE42_RESERVED_INT_PIE43_RESERVED_INT_PIE44_RESERVED_INT_PIE45_RESERVED_INT_PIE46_RESERVED_INT_PIE47_RESERVED_INT_PIE48_RESERVED_INT_PIE49_RESERVED_INT_SPIC_RX_INT_SPIC_TX_INT_PIE50_RESERVED_INT_PIE51_RESERVED_INT_PIE52_RESERVED_INT_PIE53_RESERVED_INT_PIE54_RESERVED_INT_PIE55_RESERVED_INT_PIE56_RESERVED_INT_PIE57_RESERVED_INT_PIE58_RESERVED_INT_PIE59_RESERVED_INT_PIE60_RESERVED_INT_PIE61_RESERVED_INT_PIE62_RESERVED_INT_PIE63_RESERVED_INT_PIE64_RESERVED_INT_PIE65_RESERVED_INT_PIE66_RESERVED_INT_PIE67_RESERVED_INT_PIE68_RESERVED_INT_PIE69_RESERVED_INT_UPPA_INT_PIE71_RESERVED_INT_PIE73_RESERVED_INT_PIE74_RESERVED_INT_PIE75_RESERVED_INT_PIE76_RESERVED_INT_PIE77_RESERVED_INT_PIE78_RESERVED_INT_USBA_INT_PIE80_RESERVED_INT_ADCC_EVT_INT_ADCC2_INT_ADCC3_INT_ADCC4_INT_ADCD_EVT_INT_ADCD2_INT_ADCD3_INT_ADCD4_INT_PIE81_RESERVED_INT_PIE82_RESERVED_INT_PIE83_RESERVED_INT_PIE84_RESERVED_INT_PIE85_RESERVED_INT_PIE86_RESERVED_INT_PIE87_RESERVED_INT_PIE88_RESERVED_INT_EMIF_ERROR_INT_RAM_CORRECTABLE_ERROR_INT_FLASH_CORRECTABLE_ERROR_INT_RAM_ACCESS_VIOLATION_INT_SYS_PLL_SLIP_INT_AUX_PLL_SLIP_INT_CLA_OVERFLOW_INT_CLA_UNDERFLOW_INT_PRD_BITS_PRIORITYCTRL1_BITS_CH1PRIORITY_PRIORITYCTRL1_REG_PRIORITYSTAT_BITS_ACTIVESTS_ACTIVESTS_SHADOW_PRIORITYSTAT_REG_PUMPREQUEST_BITS_PUMPREQUEST_REG_QCAPCTL_BITS_QCAPCTL_REG_QCLR_BITS_QCLR_REG_QDECCTL_BITS_QDECCTL_REG_QEINT_BITS_QEINT_REG_QEPCTL_BITS_QEPCTL_REG_QEPSTS_BITS_QEPSTS_REG_QFLG_BITS_QFLG_REG_QFRC_BITS_QFRC_REG_QPOSCTL_BITS_QPOSCTL_REG_RAMPDLYA_BITS_RAMPDLYA_REG_RAMPDLYS_BITS_RAMPDLYS_REG_RAMSTAT_BITS_STATUS_RAM0_STATUS_RAM1_STATUS_RAM2_STATUS_RAM3_STATUS_RAM4_STATUS_RAM5_STATUS_RAM6_STATUS_RAM7_STATUS_CLA1_RAMSTAT_REG_RAWINTST_BITS_RAWINTST_REG_RCR1_BITS_RCR1_REG_RCR2_BITS_RCOMPAND_RCR2_REG_RCSR_BITS_MINOR_REVISION_MAJOR_REVISION_MODULE_ID_RCSR_REG_RESC_BITS_NMIWDRSn_HIBRESETn_SCCRESETn_XRSn_pin_status_TRSTn_pin_status_RESC_REG_ROMPREFETCH_BITS_PFDISABLE_ROMPREFETCH_REG_ROMWAITSTATE_BITS_WSDISABLE_ROMWAITSTATE_REG_ROM_PREFETCH_REGS_ROMPREFETCH_ROM_WAIT_STATE_REGS_ROMWAITSTATE_RSTSTAT_BITS_CPU2NMIWDRST_CPU2HWBISTRST0_CPU2HWBISTRST1_RSTSTAT_REG_SCICCR_BITS_ADDRIDLE_MODE_LOOPBKENA_PARITYENA_STOPBITS_SCICCR_REG_SCICTL1_BITS_RXERRINTENA_SCICTL1_REG_SCICTL2_BITS_TXINTENA_RXBKINTENA_SCICTL2_REG_SCIFFCT_BITS_SCIFFCT_REG_SCIFFRX_BITS_RXFIFORESET_RXFFOVRCLR_SCIFFRX_REG_SCIFFTX_BITS_TXFIFOXRESET_SCIFFENA_SCIFFTX_REG_SCIHBAUD_BITS_SCIHBAUD_REG_SCILBAUD_BITS_SCILBAUD_REG_SCIPRI_BITS_SCIPRI_REG_SCIRXBUF_BITS_SCIRXBUF_REG_SCIRXEMU_BITS_SCIRXEMU_REG_SCIRXST_BITS_SCIRXST_REG_SCITXBUF_BITS_SCITXBUF_REG_SCI_REGS_SCIHBAUD_SCILBAUD_SCIRXEMU_SCIRXBUF_SCITXBUF_SCSR_BITS_WDOVERRIDE_SCSR_REG_SDCMPH1_BITS_SDCMPH1_REG_SDCMPH2_BITS_SDCMPH2_REG_SDCMPH3_BITS_SDCMPH3_REG_SDCMPH4_BITS_SDCMPH4_REG_SDCMPL1_BITS_SDCMPL1_REG_SDCMPL2_BITS_SDCMPL2_REG_SDCMPL3_BITS_SDCMPL3_REG_SDCMPL4_BITS_SDCMPL4_REG_SDCPARM1_BITS_SDCPARM1_REG_SDCPARM2_BITS_SDCPARM2_REG_SDCPARM3_BITS_SDCPARM3_REG_SDCPARM4_BITS_SDCPARM4_REG_SDCTLPARM1_BITS_SDCTLPARM1_REG_SDCTLPARM2_BITS_SDCTLPARM2_REG_SDCTLPARM3_BITS_SDCTLPARM3_REG_SDCTLPARM4_BITS_SDCTLPARM4_REG_SDCTL_BITS_SDCTL_REG_SDDATA1_BITS_DATA32HI_SDDATA1_REG_SDDATA2_BITS_SDDATA2_REG_SDDATA3_BITS_SDDATA3_REG_SDDATA4_BITS_SDDATA4_REG_SDDFPARM1_BITS_FILRESEN_SDDFPARM1_REG_SDDFPARM2_BITS_SDDFPARM2_REG_SDDFPARM3_BITS_SDDFPARM3_REG_SDDFPARM4_BITS_SDDFPARM4_REG_SDFM_REGS_SDIFLGCLR_SDMFILEN_SDSTATUS_SDCTLPARM1_SDDFPARM1_SDIPARM1_SDCPARM1_SDCTLPARM2_SDDFPARM2_SDIPARM2_SDCPARM2_SDCTLPARM3_SDDFPARM3_SDIPARM3_SDCPARM3_SDCTLPARM4_SDDFPARM4_SDIPARM4_SDCPARM4_SDIFLGCLR_BITS_SDIFLGCLR_REG_SDIFLG_BITS_SDIFLG_REG_SDIPARM1_BITS_SDIPARM1_REG_SDIPARM2_BITS_SDIPARM2_REG_SDIPARM3_BITS_SDIPARM3_REG_SDIPARM4_BITS_SDIPARM4_REG_SDMFILEN_BITS_SDMFILEN_REG_SDRAM_CR_BITS_PAGESIGE_BIT_11_9_LOCK_SDRAM_CR_REG_SDRAM_RCR_BITS_REFRESH_RATE_SDRAM_RCR_REG_SDRAM_TR_BITS_SDRAM_TR_REG_SDR_EXT_TMNG_BITS_SDR_EXT_TMNG_REG_SDSTATUS_BITS_SDSTATUS_REG_SECMSEL_BITS_SECMSEL_REG_SECTSTAT_BITS_STATUS_SECTA_STATUS_SECTB_STATUS_SECTC_STATUS_SECTD_STATUS_SECTE_STATUS_SECTF_STATUS_SECTG_STATUS_SECTH_STATUS_SECTI_STATUS_SECTJ_STATUS_SECTK_STATUS_SECTL_STATUS_SECTM_STATUS_SECTN_STATUS_BANK2_SECTSTAT_REG_SOFTINTEN_BITS_SOFTINTEN_REG_SOFTINTFRC_BITS_SOFTINTFRC_REG_SOFTPRES0_BITS_SOFTPRES0_REG_SOFTPRES11_BITS_SOFTPRES11_REG_SOFTPRES13_BITS_SOFTPRES13_REG_SOFTPRES14_BITS_SOFTPRES14_REG_SOFTPRES16_BITS_SOFTPRES16_REG_SOFTPRES1_BITS_SOFTPRES1_REG_SOFTPRES2_BITS_SOFTPRES2_REG_SOFTPRES3_BITS_SOFTPRES3_REG_SOFTPRES4_BITS_SOFTPRES4_REG_SOFTPRES5_BITS_SOFTPRES5_REG_SOFTPRES6_BITS_SOFTPRES6_REG_SOFTPRES7_BITS_SOFTPRES7_REG_SOFTPRES8_BITS_SOFTPRES8_REG_SOFTPRES9_BITS_SOFTPRES9_REG_SPCR1_BITS_RSYNCERR_SPCR1_REG_SPCR2_BITS_XSYNCERR_SPCR2_REG_SPIBRR_BITS_SPI_BIT_RATE_SPIBRR_REG_SPICCR_BITS_CLKPOLARITY_SPISWRESET_SPICCR_REG_SPICTL_BITS_SPIINTENA_MASTER_SLAVE_CLK_PHASE_OVERRUNINTENA_SPICTL_REG_SPIFFCT_BITS_SPIFFCT_REG_SPIFFRX_BITS_RXFFOVFCLR_SPIFFRX_REG_SPIFFTX_BITS_SPIFFENA_SPIFFTX_REG_SPIPRI_BITS_PRIORITY_SPIPRI_REG_SPISTS_BITS_BUFFULL_FLAG_INT_FLAG_OVERRUN_FLAG_SPISTS_REG_SPI_REGS_SPIRXEMU_SPIRXBUF_SPITXBUF_SRGR1_BITS_SRGR1_REG_SRGR2_BITS_SRGR2_REG_SYNCSELECT_BITS_EPWM4SYNCIN_EPWM7SYNCIN_EPWM10SYNCIN_ECAP1SYNCIN_ECAP4SYNCIN_SYNCSELECT_REG_SYNCSOCLOCK_BITS_SYNCSELECT_EXTADCSOCSELECT_SYNCSOCLOCK_REG_SYSCLKDIVSEL_BITS_PLLSYSCLKDIV_SYSCLKDIVSEL_REG_SYSPLLCTL1_BITS_SYSPLLCTL1_REG_SYSPLLMULT_BITS_SYSPLLMULT_REG_SYSPLLSTS_BITS_SYSPLLSTS_REG_TBCTL2_BITS_SELFCLRTRREM_OSHTSYNCMODE_OSHTSYNC_SYNCOSELX_PRDLDSYNC_TBCTL2_REG_TBCTL_BITS_SYNCOSEL_HSPCLKDIV_TBCTL_REG_TBPHS_BITS_TBPHS_REG_TBSTS_BITS_TBSTS_REG_TCR_BITS_THCFG_BITS_THCFG_REG_TIM_BITS_TMR2CLKCTL_BITS_TMR2CLKSRCSEL_TMR2CLKPRESCALE_TMR2CLKCTL_REG_TPRH_BITS_TPRH_REG_TPR_BITS_TRIG_REGS_SYNCSOCLOCK_TRIP10MUX0TO15CFG_BITS_TRIP10MUX0TO15CFG_REG_TRIP10MUX16TO31CFG_BITS_TRIP10MUX16TO31CFG_REG_TRIP10MUXENABLE_BITS_TRIP10MUXENABLE_REG_TRIP11MUX0TO15CFG_BITS_TRIP11MUX0TO15CFG_REG_TRIP11MUX16TO31CFG_BITS_TRIP11MUX16TO31CFG_REG_TRIP11MUXENABLE_BITS_TRIP11MUXENABLE_REG_TRIP12MUX0TO15CFG_BITS_TRIP12MUX0TO15CFG_REG_TRIP12MUX16TO31CFG_BITS_TRIP12MUX16TO31CFG_REG_TRIP12MUXENABLE_BITS_TRIP12MUXENABLE_REG_TRIP4MUX0TO15CFG_BITS_TRIP4MUX0TO15CFG_REG_TRIP4MUX16TO31CFG_BITS_TRIP4MUX16TO31CFG_REG_TRIP4MUXENABLE_BITS_TRIP4MUXENABLE_REG_TRIP5MUX0TO15CFG_BITS_TRIP5MUX0TO15CFG_REG_TRIP5MUX16TO31CFG_BITS_TRIP5MUX16TO31CFG_REG_TRIP5MUXENABLE_BITS_TRIP5MUXENABLE_REG_TRIP7MUX0TO15CFG_BITS_TRIP7MUX0TO15CFG_REG_TRIP7MUX16TO31CFG_BITS_TRIP7MUX16TO31CFG_REG_TRIP7MUXENABLE_BITS_TRIP7MUXENABLE_REG_TRIP8MUX0TO15CFG_BITS_TRIP8MUX0TO15CFG_REG_TRIP8MUX16TO31CFG_BITS_TRIP8MUX16TO31CFG_REG_TRIP8MUXENABLE_BITS_TRIP8MUXENABLE_REG_TRIP9MUX0TO15CFG_BITS_TRIP9MUX0TO15CFG_REG_TRIP9MUX16TO31CFG_BITS_TRIP9MUX16TO31CFG_REG_TRIP9MUXENABLE_BITS_TRIP9MUXENABLE_REG_TRIPLOCK_BITS_TRIPLOCK_REG_TRIPOUTINV_BITS_TRIPOUTINV_REG_TSNSCTL_BITS_TSNSCTL_REG_TZCBCCLR_BITS_TZCBCCLR_REG_TZCBCFLG_BITS_TZCBCFLG_REG_TZCLR_BITS_CBCPULSE_TZCLR_REG_TZCTL2_BITS_TZCTL2_REG_TZCTLDCA_BITS_DCAEVT1U_DCAEVT1D_DCAEVT2U_DCAEVT2D_TZCTLDCA_REG_TZCTLDCB_BITS_DCBEVT1U_DCBEVT1D_DCBEVT2U_DCBEVT2D_TZCTLDCB_REG_TZCTL_BITS_TZCTL_REG_TZDCSEL_BITS_TZDCSEL_REG_TZEINT_BITS_TZEINT_REG_TZFLG_BITS_TZFLG_REG_TZFRC_BITS_TZFRC_REG_TZOSTCLR_BITS_TZOSTCLR_REG_TZOSTFLG_BITS_TZOSTFLG_REG_TZSEL_BITS_TZSEL_REG_UCERRCLR_BITS_UCERRCLR_REG_UCERRFLG_BITS_UCERRFLG_REG_UCERRSET_BITS_UCERRSET_REG_UPP_REGS_RAWINTST_INTENSET_INTENCLR_CHIDESC0_CHIDESC1_CHIDESC2_CHQDESC0_CHQDESC1_CHQDESC2_WDCNTR_BITS_WDCNTR_REG_WDCR_BITS_WDCR_REG_WDKEY_BITS_WDKEY_REG_WDWCR_BITS_FIRSTKEY_WDWCR_REG_X1CNT_BITS_X1CNT_REG_XBARCLR1_BITS_CMPSS1_CTRIPL_CMPSS1_CTRIPH_CMPSS2_CTRIPL_CMPSS2_CTRIPH_CMPSS3_CTRIPL_CMPSS3_CTRIPH_CMPSS4_CTRIPL_CMPSS4_CTRIPH_CMPSS5_CTRIPL_CMPSS5_CTRIPH_CMPSS6_CTRIPL_CMPSS6_CTRIPH_CMPSS7_CTRIPL_CMPSS7_CTRIPH_CMPSS8_CTRIPL_CMPSS8_CTRIPH_CMPSS1_CTRIPOUTL_CMPSS1_CTRIPOUTH_CMPSS2_CTRIPOUTL_CMPSS2_CTRIPOUTH_CMPSS3_CTRIPOUTL_CMPSS3_CTRIPOUTH_CMPSS4_CTRIPOUTL_CMPSS4_CTRIPOUTH_CMPSS5_CTRIPOUTL_CMPSS5_CTRIPOUTH_CMPSS6_CTRIPOUTL_CMPSS6_CTRIPOUTH_CMPSS7_CTRIPOUTL_CMPSS7_CTRIPOUTH_CMPSS8_CTRIPOUTL_CMPSS8_CTRIPOUTH_XBARCLR1_REG_XBARCLR2_BITS_ECAP1_OUT_ECAP2_OUT_ECAP3_OUT_ECAP4_OUT_ECAP5_OUT_ECAP6_OUT_EXTSYNCOUT_ADCAEVT1_ADCAEVT2_ADCAEVT3_ADCAEVT4_ADCBEVT1_ADCBEVT2_ADCBEVT3_ADCBEVT4_ADCCEVT1_XBARCLR2_REG_XBARCLR3_BITS_ADCCEVT2_ADCCEVT3_ADCCEVT4_ADCDEVT1_ADCDEVT2_ADCDEVT3_ADCDEVT4_SD1FLT1_COMPL_SD1FLT1_COMPH_SD1FLT2_COMPL_SD1FLT2_COMPH_SD1FLT3_COMPL_SD1FLT3_COMPH_SD1FLT4_COMPL_SD1FLT4_COMPH_SD2FLT1_COMPL_SD2FLT1_COMPH_SD2FLT2_COMPL_SD2FLT2_COMPH_SD2FLT3_COMPL_SD2FLT3_COMPH_SD2FLT4_COMPL_SD2FLT4_COMPH_XBARCLR3_REG_XB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_15_02__FBPROT_Reserved_31_16__FBSE_Reserved_31_16__FBBUSY_Reserved_15_08__FBBUSY_Reserved_31_06_OTPPROTDIS__FBAC_Reserved_31_24_BANKPWR0_BANKPWR1_BANKPWR2_BANKPWR3_BANKPWR4_BANKPWR5_BANKPWR6_BANKPWR7_REG_PWRSAV__FBAC_Reserved_23_20_FSM_PWRSAV__FBAC_Reserved_31_28__FBPRDY_Reserved_14_08_BANKBUSY__FBPRDY_Reserved_31_24__FBAC1_Reserved_15_01_PSLEEPTDIS__FBAC1_Reserved_31_27__FBAC2_Reserved_31_16__FMAC_Reserved_15_03__FMAC_Reserved_31_15__FMSTAT_Reserved_31_18__FEMU_ECC_Reserved_15_08__FEMU_ECC_Reserved_31_16__FLOCK_Reserved_31_16_EMU_ADDR_15_0_EMU_ADDR_21_16__FEMU_ADDR_Reserved_31_22_DIAGMODE__FDIAGCTRL_Reserved_07_03_DIAG_BUF_SEL__FDIAGCTRL_Reserved_11_10_DIAG_ECC_SEL__FDIAGCTRL_Reserved_15_DIAG_EN_KEY__FDIAGCTRL_Reserved_23_20_DIAG_TRIG__FDIAGCTRL_Reserved_31_25__FRAW_ECC_Reserved_15_08__FRAW_ECC_Reserved_31_16_DAT_INV_PAR_ADD_INV_PAR_PAR_OVR_KEY_BUS_PAR_DIS_BNK_INV_PAR__FPAR_OVR_Reserved_31_17__FVREADCT_Reserved_15_04__FVREADCT_Reserved_31_16_VHVCT_PV__FVHVCT1_Reserved_15_09__FVHVCT1_Reserved_31_25__FVHVCT2_Reserved_15_09__FVHVCT2_Reserved_31_25_VHVCT_READ__FVHVCT3_Reserved_15_09__FVHVCT3_Reserved_31_20__FVNVCT_Reserved_07_05_VCG2P5CT__FVNVCT_Reserved_15_13__FVNVCT_Reserved_31_16__FVLSP_Reserved_11_00__FVLSP_Reserved_31_16__FVWLCT_Reserved_15_05__FVWLCT_Reserved_31_16_EFUSE_EN__FEFUSECTRL_Reserved_07_05__FEFUSECTRL_Reserved_15_09_WRITE_EN__FEFUSECTRL_Reserved_23_18_CHAIN_SEL__FEFUSECTRL_Reserved_31_27_SHIFT_DONE__FEFUSE_Reserved_15_01__FEFUSE_Reserved_31_16_SEQ_PUMP__FSEQPMP_Reserved_15_08__FSEQPMP_Reserved_31_15_CLK_TRIM_0_15_CLK_TRIM_18_16__FCLKTRIM_Reserved_31_19_SectorID2__FEDACSDIS2_Reserved_4_SectorID2_inverse__FEDACSDIS2_Reserved_12_BankID2_inverse_SectorID3__FEDACSDIS2_Reserved_20_SectorID3_inverse__FEDACSDIS2_Reserved_28_BankID3_inverse__FBSTROBES_Reserved_01_00_NOCOLRED__FBSTROBES_Reserved_07__FBSTROBES_Reserved_15_9__FBSTROBES_Reserved_23_17__FBSTROBES_Reserved_31_25__5VPWRDNZ__3VPWRDNZ__FBSTROBES_Reserved_07_02_EXECUTEZ__FPSTROBES_Reserved_15_09__FPSTROBES_Reserved_31_16__FBMODE_Reserved_15_03__FBMODE_Reserved_31_16__FTCR_Reserved_15_07__FTCR_Reserved_31_16_ADDR_INCR_TP_BUSY_SEL_FL_DATAIN_SEL_TP_DATA_SEL_WDAT_CHANGE__FPMT_CTRL_Reserved_31_21_PBIST_KEY__PBIST_CTRL_Reserved_15_05__PBIST_CTRL_Reserved_31_16__FTCTRL_Reserved_00__FTCTRL_Reserved_15_02_WDATA_BLK_CLR__FTCTRL_Reserved_23_17_AUTOCALC_EN__FTCTRL_Reserved_31_25_WPDATA_287_256_u8Bytes31_24_u8Bytes23_16_u8Bytes15_08_u8Bytes07_00__FSWSTAT_Reserved_15_01__FSWSTAT_Reserved_31_16__FSM_GLBCTRL_Reserved_15_01__FSM_GLBCTRL_Reserved_31_16__FSM_STATE_Reserved_05_00_TIOTP_ACT__FSM_STATE_Reserved_09__FSM_STATE_Reserved_15_12__FSM_STATE_Reserved_31_16_OVR_PUL_CNT__FSM_STATUS_Reserved_15_03__FSM_STATUS_Reserved_31_16__FSM_COMMAND_Reserved_15_06__FSM_COMMAND_Reserved_31_16__FSM_PE_OSU_Reserved_31_16__FSM_VSTAT_Reserved_11_00_VSTAT_CNT__FSM_VSTAT_Reserved_31_16__FSM_PE_VSU_Reserved_31_16__FSM_CMP_VSU_Reserved_31_16_EXE_VALD__FSM_EX_VAL_Reserved_31_16__FSM_RD_H_Reserved_15_08__FSM_RD_H_Reserved_31_16__FSM_P_OH_Reserved_07_00__FSM_P_OH_Reserved_31_16__FSM_ERA_OH_Reserved_31_16_SAV_P_PUL__FSM_SAV_PPUL_Reserved_15_12__FSM_SAV_PPUL_Reserved_31_16__FSM_PE_VH_Reserved_31_16_PROG_PUL_WIDTH__FSM_PRG_PW_Reserved_31_16_SAV_ERA_PUL__FSM_SAV_ERA_PUL_Reserved_15_12__FSM_SAV_ERA_PUL_Reserved_31_16_SAV_ERA_MODE_SAV_PGM_CMD_ERA_SUBMODE_PGM_SUBMODE_RDV_SUBMODE__FSM_MODE_Reserved_31_20_PGM_ADDR_15_0_PGM_ADDR_22_16_PGM_BANK__FSM_PGM_Reserved_27_26_ERA_ADDR_15_0_ERA_ADDR_22_16_ERA_BANK__FSM_ERA_Reserved_31_26_MAX_PRG_PUL__FSM_PRG_PUL_Reserved_15_12_BEG_EC_LEVEL__FSM_PRG_PUL_Reserved_31_25_MAX_ERA_PUL__FSM_ERA_PUL_Reserved_15_12_MAX_EC_LEVEL__FSM_ERA_PUL_Reserved_31_25__FSM_STEP_SIZE_Reserved_15_00_EC_STEP_SIZE__FSM_STEP_SIZE_Reserved_31_25_PUL_CNTR__FSM_PUL_CNTR_Reserved_15_12_CUR_EC_LEVEL__FSM_PUL_CNTR_Reserved_31_25_EC_STEP_HEIGHT__FSM_EC_STEP_HEIGHT_Reserved_15_7__FSM_EC_STEP_HEIGHT_Reserved_31_16_OVERRIDE_INV_DATA_DIS_TST_EN_PREC_STOP_EN_PGM_SEC_COF_EN_BNK_ERA_MODE_DBG_SHORT_ROW_DO_REDU_COL__FSM_ST_MACHINE_Reserved_12_RESTRT_ADDR_ONE_TIME_GOOD__FSM_ST_MACHINE_Reserved_15_RV_INT_EN_RV_SEC_EN_CMPV_ALLOWED_ALL_BANKS_FSM_INT_EN_DO_PRECOND__FSM_ST_MACHINE_Reserved_31_24__FSM_WR_ENA_Reserved_15_03__FSM_WR_ENA_Reserved_31_16__FSM_ACC_EP_Reserved_31_16__FSM_SECTOR_Reserved_15_08_SECT_ERASED_CONFIG_CRC_MOD_VERSION_15_12_MOD_VERSION_31_16_FSMEXECUTE__FSM_EXECUTE_Reserved_15_05_SUSPEND_NOW__FSM_EXECUTE_Reserved_31_20_AUTOSTART_GRACE_AUTOSUSP_EN__EEPROM_CONFIG_Reserved_15_09__EEPROM_CONFIG_Reserved_31_20_MAIN_NUM_BANK_MAIN_BANK_WIDTH_EE_NUM_BANK_EE_BANK_WIDTH_CPU_TYPE1_AUTO_SUSP_EE_IN_MAIN_AUTOCALC__FCFG_WRAPPER_Reserved_23_22_FAMILY_TYPE_B0_START_ADDR_0_15_B0_START_ADDR_16_23_B0_MUX_FACTOR_B0_MAX_SECTOR_B1_START_ADDR_0_15_B1_START_ADDR_16_23_B1_MUX_FACTOR_B1_MAX_SECTOR_B2_START_ADDR_0_15_B2_START_ADDR_16_23_B2_MUX_FACTOR_B2_MAX_SECTOR_B3_START_ADDR_0_15_B3_START_ADDR_16_23_B3_MUX_FACTOR_B3_MAX_SECTOR_B4_START_ADDR_0_15_B4_START_ADDR_16_23_B4_MUX_FACTOR_B4_MAX_SECTOR_B5_START_ADDR_0_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