//-------------------------------------------------------//
//        Project Code : ALE300K03-21-LGE-GEN2.0-BE-CPU1
//           File Name : FaultDefine.h
//          Created on : 2022. 10. 30.
//         Description :
//              Author : KimJeongWoo
//  Last modified Date :
//-------------------------------------------------------//

#ifndef MAIN_RESOURCE_INCLUDE_FAULTDEFINE_H_
#define MAIN_RESOURCE_INCLUDE_FAULTDEFINE_H_

#ifdef __cplusplus
extern "C" {
#endif

struct sFAULT_SW_LIST1
{
	Uint32 CH1_UV_OV :1;		//  0x00000001
	Uint32 CH1_VIS_OV :1;		//  0x00000002
	Uint32 CH1_IR_OV :1;		        //	0x00000004

	Uint32 CH2_UV_OV :1;               //  0x00000008
	Uint32 CH2_VIS_OV :1;  		//  0x00000010
	Uint32 CH2_IR_OV :1;         //  0x00000020

	Uint32 CH3_UV_OV :1;         //  0x00000040
	Uint32 CH3_VIS_OV :1;         //  0x00000080
	Uint32 CH3_IR_OV :1;			//  0x00000100

	Uint32 CH4_UV_OV :1;          //  0x00000200
	Uint32 CH4_VIS_OV :1;            //  0x00000400
    Uint32 CH4_IR_OV :1;           //  0x00000800

	Uint32 Reseved0 :20;			    //  0x08000000 ~ 0x80000000

};

union uFAULT_SW1
{
	Uint32 all;
	struct sFAULT_SW_LIST1 bit;
};

struct sFAULT_SW_LIST2
{

	//contactType Fault
	Uint32 Switch_EmergencyStop :1;		// 0x00000001
//	Uint32 Switch_Paddlelock :1;		// 0x00000002 Paddle lock switch or Limit �switch
//	Uint32 FuseAcAphase :1;				// 0x00000004
//	Uint32 FuseAcBphase :1;				// 0x00000008
//	Uint32 FuseAcCphase :1;				// 0x00000010
//	Uint32 FuseDc :1;					// 0x00000020
//
//	Uint32 SpdCtrl :1;					// 0x00000040
//	Uint32 SpdPower :1;				    // 0x00000080
//
//	Uint32 FanBeOutStackFrontTop :1;	// 0x00000100
//	Uint32 FanBeOutStackFrontBot :1;	// 0x00000200
//	Uint32 FanMcStackFront :1;			// 0x00000400
//	Uint32 FanMcStackRear :1;			// 0x00000800
//	Uint32 FanCpRearLeft :1;			// 0x00001000
//	Uint32 FanCpRearRight :1;			// 0x00002000
//	Uint32 FanRackLeft :1;				// 0x00004000
//	Uint32 FanRackRight :1;			    // 0x00008000
//	Uint32 FanBeStackFront :1;			// 0x00010000
//	Uint32 FanBeStackRear :1;			// 0x00020000
//
//	Uint32 OT_ThsBeStackLeft :1;		// 0x00040000  //Thermal Switch
//	Uint32 OT_ThsBeStackRight :1;		// 0x00080000  //Thermal Switch
//
//	Uint16 Cmc :1;               		// 0x00100000  //Cmc
//	Uint16 Mmc :1;              		// 0x00200000  //Mmc
//	Uint16 Mccb_Open :1;				// 0x00400000  // MCCB
//
//	Uint16 OT_Ntc_Dcl :1;				// 0x00800000 //
//	Uint16 OT_Ntc_Acl :1;				// 0x01000000 //
//	Uint16 OT_Ntc_Tr :1;				// 0x02000000 //
//
//	Uint16 OT_Ntc_SicConvA :1;			// 0x04000000 //
//	Uint16 OT_Ntc_SicConvB :1;			// 0x08000000 //
//	Uint16 OT_Ntc_SicConvC :1;			// 0x10000000 //
//
//	Uint16 OT_Ntc_SicInvA :1;			// 0x20000000 //
//	Uint16 OT_Ntc_SicInvB :1;			// 0x40000000 //
//	Uint16 OT_Ntc_SicInvC :1;			// 0x80000000 //

};

union uFAULT_SW2
{
	Uint32 all;
	struct sFAULT_SW_LIST2 bit;
};

struct sFAULT_SW_LIST3 //
{
    Uint32 Comm_RTU :1;                 // 0x00000001
    Uint32 Comm_Can :1;                 // 0x00000002
//	Uint32 Offset_Iabc :1;         // 0x00000001
//	Uint32 Offset_IL :1;         // 0x00000002
//	Uint32 Offset_Ibe :1;         // 0x00000004
//
//	Uint32 Err_Nvram :1; 		// 0x00000008
//	Uint32 Comm_CanMe :1;  		// 0x00000010
//	Uint32 Comm_CanBe :1;         // 0x00000020
//
//	Uint32 Err_Parallel :1;

	Uint32 :30;
};

union uFAULT_SW3
{
	Uint32 all;
	struct sFAULT_SW_LIST3 bit;
};

struct sFault
{
	union uFAULT_SW1 Sw1; //32bit
	union uFAULT_SW2 Sw2; //32bit
	union uFAULT_SW3 Sw3; //32bit
};

struct sFaultSet
{
	float Ratio;
	float SetLevel;
	float SetTime;
	int SetCnt;
	int ChkCnt; // Check Count
	int SetStableCnt;
	int StableCnt;
};

#pragma SET_DATA_SECTION(".Fault")

extern struct sFault Fault;

extern struct sFaultSet FT_UV_OV;
extern struct sFaultSet FT_VIS_OV;
extern struct sFaultSet FT_IR_OV;

extern struct sFaultSet OtNtc5;
extern struct sFaultSet OtNtc6;

extern struct sMesureList FaultLatch;

#pragma SET_DATA_SECTION()

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* MAIN_RESOURCE_INCLUDE_FAULTDEFINE_H_ */