MEMORY { PAGE 0 : /* Program Memory */ /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ /* BEGIN is used for the "boot to Flash" bootloader mode */ BEGIN : origin = 0x080000, length = 0x000002 RAMLS012 : origin = 0x008000, length = 0x001800 // RAMLS1 : origin = 0x008800, length = 0x000800 // RAMLS2 : origin = 0x009000, length = 0x000800 RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ // RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RESET : origin = 0x3FFFC0, length = 0x000002 /* Flash sectors */ FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ // FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ PAGE 1 : /* Data Memory */ /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */ RAMM0 : origin = 0x000123, length = 0x0002DD RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ // RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ RAMD0 : origin = 0x00B000, length = 0x000800 RAMD1 : origin = 0x00B800, length = 0x000800 RAMLS3 : origin = 0x009800, length = 0x000800 RAMLS4 : origin = 0x00A000, length = 0x000800 RAMLS5 : origin = 0x00A800, length = 0x000800 RAMGS0 : origin = 0x00C000, length = 0x001000 RAMGS1 : origin = 0x00D000, length = 0x001000 RAMGS2 : origin = 0x00E000, length = 0x001000 RAMGS345 : origin = 0x00F000, length = 0x003000 // RAMGS4 : origin = 0x010000, length = 0x001000 // RAMGS5 : origin = 0x011000, length = 0x001000 RAMGS6 : origin = 0x012000, length = 0x001000 //CPU2 RAMGS7 : origin = 0x013000, length = 0x001000 RAMGS8 : origin = 0x014000, length = 0x001000 RAMGS9 : origin = 0x015000, length = 0x001000 RAMGS10 : origin = 0x016000, length = 0x001000 RAMGS11 : origin = 0x017000, length = 0x001000 RAMGS12 : origin = 0x018000, length = 0x001000 RAMGS13 : origin = 0x019000, length = 0x001000 CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ } SECTIONS { /* Allocate program areas: */ .cinit : > FLASHB PAGE = 0, ALIGN(8) .pinit : > FLASHB, PAGE = 0, ALIGN(8) .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8) codestart : > BEGIN PAGE = 0, ALIGN(8) /* Allocate uninitalized data sections: */ .stack : > RAMM1 PAGE = 1 .ebss : >> RAMLS3 | RAMLS4 | RAMLS5 , PAGE = 1 .esysmem : > RAMLS5, PAGE = 1 .cio : > RAMLS5, PAGE = 1 /* Initalized sections go in Flash */ .econst : >> FLASHF PAGE = 0, ALIGN(8) .switch : > FLASHB PAGE = 0, ALIGN(8) .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ .TI.ramfunc : {} LOAD = FLASHD, RUN = RAMLS012, LOAD_START(_RamfuncsLoadStart), LOAD_SIZE(_RamfuncsLoadSize), LOAD_END(_RamfuncsLoadEnd), RUN_START(_RamfuncsRunStart), RUN_SIZE(_RamfuncsRunSize), RUN_END(_RamfuncsRunEnd), PAGE = 0, ALIGN(8) FPUmathTables : {} LOAD = FLASHN, RUN = RAMD0, RUN_START(_FPUmathTablesRunStart), LOAD_START(_FPUmathTablesLoadStart), LOAD_SIZE(_FPUmathTablesLoadSize), PAGE = 1, ALIGN(8) MSGRAM_CPU1_TO_CPU2 : > CPU1TOCPU2RAM, PAGE = 1 MSGRAM_CPU2_TO_CPU1 : > CPU2TOCPU1RAM, PAGE = 1 // DMARAM1 : > RAMGS5, PAGE = 1 // DMARAM2 : > RAMGS5, PAGE = 1 // DMARAM3 : > RAMGS5, PAGE = 1 // DMARAM4 : > RAMGS5, PAGE = 1 //-------------------------------------------------------------// //only Cpu1 can access .CpuInfo : > RAMLS5, PAGE = 1 .TimeSharing : > RAMLS5, PAGE = 1 //-------------------------------------------------------------// //CPU1 Access Only Memory .DigitalFilter : > RAMLS3, PAGE = 1 .Relay : > RAMLS3, PAGE = 1 .OffsetProcess : > RAMLS3, PAGE = 1 .Pll : > RAMLS3, PAGE = 1 .RunStopSeq : > RAMLS3, PAGE = 1 .FaultProcess : > RAMLS3, PAGE = 1 .IinvCtrl : > RAMLS4, PAGE = 1 .IinvHarResCtrl : > RAMLS4, PAGE = 1 .VdcCtrl : > RAMLS4, PAGE = 1 .IbatCtrl : > RAMLS4, PAGE = 1 .VbatCtrl : > RAMLS4, PAGE = 1 .VdabCtrl : > RAMLS4, PAGE = 1 .VboostCtrl : > RAMLS4, PAGE = 1 .IdabCtrl : > RAMLS4, PAGE = 1 .SoftStart : > RAMLS4, PAGE = 1 //Temp .Trace : > RAMGS345, PAGE = 1 //CPU1 RW, CPU2 R Memory .AdcLib : > RAMGS6, PAGE = 1 .SystemVar : > RAMGS6, PAGE = 1 .Fault : > RAMGS6, PAGE = 1 .Scale : > RAMGS6, PAGE = 1 .Status : > RAMGS6, PAGE = 1 .IntTemp : > RAMGS6, PAGE = 1 .ModbusData : > RAMGS6, PAGE = 1 //CPU2 RW, CPU1 R Memory .RmsAvg : > RAMGS13, PAGE = 1 .TempData : > RAMGS13, PAGE = 1 .CanLib : > RAMGS13, PAGE = 1 .CanCHAData : > RAMGS13, PAGE = 1 .Modbus : > RAMGS13, PAGE = 1 //-------------------------------------------------------------// /* The following section definitions are required when using the IPC API Drivers */ GROUP : > CPU1TOCPU2RAM, PAGE = 1 { PUTBUFFER PUTWRITEIDX GETREADIDX } GROUP : > CPU2TOCPU1RAM, PAGE = 1 { GETBUFFER : TYPE = DSECT GETWRITEIDX : TYPE = DSECT PUTREADIDX : TYPE = DSECT } } /* //=========================================================================== // End of file. //=========================================================================== */