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//-------------------------------------------------------//
// Project Code : V2H6K01-23-ENEMAN
// File Name : SelectCPU.cpp
// Created on : 2023. 8. 8.
// Description :
// Author : KimJeongWoo
// Last modified Date :
//-------------------------------------------------------//
#include "Cpu1DeviceDefine.h"
void SetCPU2ForPeripheral()
{
InitSciGpio();
// SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_SCIB, SYSCTL_CPUSEL_CPU2);
// SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_SCIC, SYSCTL_CPUSEL_CPU2);
// SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_SCID, SYSCTL_CPUSEL_CPU2);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_SCIB, SYSCTL_CPUSEL_CPU1);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_SCIC, SYSCTL_CPUSEL_CPU1);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_SCID, SYSCTL_CPUSEL_CPU1);
InitCanGpio();
// SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_CANA, SYSCTL_CPUSEL_CPU2);
// SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_CANB, SYSCTL_CPUSEL_CPU2);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_CANA, SYSCTL_CPUSEL_CPU1);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_CANB, SYSCTL_CPUSEL_CPU1);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_ADCA, SYSCTL_CPUSEL_CPU1);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_ADCB, SYSCTL_CPUSEL_CPU1);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_ADCC, SYSCTL_CPUSEL_CPU1);
SysCtl_selectCPUForPeripheralInstance(SYSCTL_CPUSEL_ADCD, SYSCTL_CPUSEL_CPU1);
}
void SetCPU2ForGsRam()
{
// MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS7, MEMCFG_GSRAMMASTER_CPU2);
// MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS8, MEMCFG_GSRAMMASTER_CPU2);
// MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS9, MEMCFG_GSRAMMASTER_CPU2);
// MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS10, MEMCFG_GSRAMMASTER_CPU2);
// MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS11, MEMCFG_GSRAMMASTER_CPU2);
// MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS12, MEMCFG_GSRAMMASTER_CPU2);
// MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS13, MEMCFG_GSRAMMASTER_CPU2);
MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS7, MEMCFG_GSRAMMASTER_CPU1);
MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS8, MEMCFG_GSRAMMASTER_CPU1);
MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS9, MEMCFG_GSRAMMASTER_CPU1);
MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS10, MEMCFG_GSRAMMASTER_CPU1);
MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS11, MEMCFG_GSRAMMASTER_CPU1);
MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS12, MEMCFG_GSRAMMASTER_CPU1);
MemCfg_setGSRAMMasterSel(MEMCFG_SECT_GS13, MEMCFG_GSRAMMASTER_CPU1);
}
void InitCanGpio()
{
EALLOW;
GPIO_setMasterCore(18, GPIO_CORE_CPU2);
GPIO_setMasterCore(19, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_18_CANRXA);
GPIO_setPinConfig(GPIO_19_CANTXA);
GPIO_setMasterCore(21, GPIO_CORE_CPU2);
GPIO_setMasterCore(20, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_21_CANRXB);
GPIO_setPinConfig(GPIO_20_CANTXB);
EDIS;
}
void InitSciGpio()
{
//SCIB
GPIO_setMasterCore(71, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_71_SCIRXDB);
GPIO_setDirectionMode(71, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(71, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC);
GPIO_setMasterCore(70, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_70_SCITXDB);
GPIO_setDirectionMode(70, GPIO_DIR_MODE_OUT);
GPIO_setPadConfig(70, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC);
//SCIC
GPIO_setMasterCore(139, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_139_SCIRXDC);
GPIO_setDirectionMode(139, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(139, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(139, GPIO_QUAL_ASYNC);
GPIO_setMasterCore(140, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_140_SCITXDC);
GPIO_setDirectionMode(140, GPIO_DIR_MODE_OUT);
GPIO_setPadConfig(140, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(140, GPIO_QUAL_ASYNC);
//SCID
GPIO_setMasterCore(105, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_105_SCIRXDD);
GPIO_setDirectionMode(105, GPIO_DIR_MODE_IN);
GPIO_setPadConfig(105, GPIO_PIN_TYPE_PULLUP);
GPIO_setQualificationMode(105, GPIO_QUAL_ASYNC);
GPIO_setMasterCore(104, GPIO_CORE_CPU2);
GPIO_setPinConfig(GPIO_104_SCITXDD);
GPIO_setDirectionMode(104, GPIO_DIR_MODE_OUT);
GPIO_setPadConfig(104, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(104, GPIO_QUAL_ASYNC);
}