//-------------------------------------------------------// // Project Code : ESS100K3L-01-19 // File Name : Epwm.cpp // Created on : 2019. 06. 07 // Description : // Author : KimJeongWoo // Last modified Date : //-------------------------------------------------------// #include <CommonLib.h> void InitEPwm1(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0.; EALLOW; //EPwm1Regs.TBPRD = Pwm_prd; // Set timer period EPwm1Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm1Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm1Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // load on CTR=Zero EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; // load on CTR=Zero EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_PRD; EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; EPwm1Regs.ETPS.bit.INTPRD = ET_2ND; EPwm1Regs.ETPS.bit.SOCPSSEL = 0; EPwm1Regs.ETPS.bit.SOCAPRD = ET_2ND; EPwm1Regs.ETPS.bit.SOCBPRD = ET_2ND; // EPwm1Regs.ETSOCPS.bit.SOCAPRD2 = 1; EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTR_PRD; EPwm1Regs.ETSEL.bit.SOCAEN = 1; EPwm1Regs.ETSEL.bit.SOCBSEL = ET_CTR_ZERO; EPwm1Regs.ETSEL.bit.SOCBEN = 1; // Set actions EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm1Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm1Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm1Regs.CMPA.bit.CMPA = 0; EPwm1Regs.CMPB.bit.CMPB = 0; EPwm1Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm1Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm1Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm1Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm1Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm1Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); EPwm1Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm1Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm2(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm2Regs.TBPRD = Pwm_prd; // Set timer period EPwm2Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm2Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm2Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // load on CTR=Zero EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; // load on CTR=Zero // EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm2Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm2Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm2Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm2Regs.CMPA.bit.CMPA = 0; EPwm2Regs.CMPB.bit.CMPB = 0; EPwm2Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm2Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm2Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm2Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm2Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count : 1 Up-Down : 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm2Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); EPwm2Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm2Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm3(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm3Regs.TBPRD = Pwm_prd; // Set timer period EPwm3Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm3Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm3Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP; EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // load on CTR=Zero EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; // load on CTR=Zero // EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm3Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm3Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm3Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm3Regs.CMPA.bit.CMPA = 0; EPwm3Regs.CMPB.bit.CMPB = 0; EPwm3Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm3Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm3Regs.DBRED = Inv_Deadtime_prd; // EPwm3Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm3Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm3Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm3Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm3Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm3Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm3Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm3Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm4(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm4Regs.TBPRD = Pwm_prd; // Set timer period EPwm4Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm4Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm4Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // load on CTR=Zero EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; // load on CTR=Zero // EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm4Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm4Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm4Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm4Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm4Regs.CMPA.bit.CMPA = 0; EPwm4Regs.CMPB.bit.CMPB = 0; EPwm4Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm4Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm4Regs.DBRED = Inv_Deadtime_prd; // EPwm4Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm4Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm4Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm4Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm4Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm4Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm4Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm4Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm5(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm5Regs.TBPRD = Pwm_prd; // Set timer period EPwm5Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm5Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm5Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // load on CTR=Zero EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; // load on CTR=Zero // EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm5Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm5Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm5Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A EPwm5Regs.AQCTLA.bit.CAD = AQ_CLEAR; // EPwm5Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm5Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm5Regs.CMPA.bit.CMPA = 0; EPwm5Regs.CMPB.bit.CMPB = 0; EPwm5Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm5Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm5Regs.DBRED = Inv_Deadtime_prd; // EPwm5Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm5Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm5Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm5Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm5Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm5Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm5Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm5Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm6(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm6Regs.TBPRD = Pwm_prd; // Set timer period EPwm6Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm6Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm6Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD; // load on CTR=Zero EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_PRD; // load on CTR=Zero // EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm6Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm6Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm6Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm6Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm6Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm6Regs.CMPA.bit.CMPA = 0; EPwm6Regs.CMPB.bit.CMPB = 0; EPwm6Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm6Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm6Regs.DBRED = Inv_Deadtime_prd; // EPwm6Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm6Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm6Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm6Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm6Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm6Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm6Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm6Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm7(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm7Regs.TBPRD = Pwm_prd; // Set timer period EPwm7Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm7Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm7Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm7Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero // EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm7Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm7Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm7Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm7Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm7Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm7Regs.CMPA.bit.CMPA = 0; EPwm7Regs.CMPB.bit.CMPB = 0; EPwm7Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm7Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm7Regs.DBRED = Inv_Deadtime_prd; // EPwm7Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm7Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm7Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm7Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm7Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm7Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm7Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm7Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm8(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm8Regs.TBPRD = Pwm_prd; // Set timer period EPwm8Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm8Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm8Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm8Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm8Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm8Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero // EPwm8Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm8Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm8Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm8Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm8Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm8Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm8Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm8Regs.CMPA.bit.CMPA = 0; EPwm8Regs.CMPB.bit.CMPB = 0; EPwm8Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm8Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm8Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm8Regs.DBRED = Inv_Deadtime_prd; // EPwm8Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm8Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm8Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm8Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm8Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm8Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm8Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm8Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm9(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm9Regs.TBPRD = Pwm_prd; // Set timer period EPwm9Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm9Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm9Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm9Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm9Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm9Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm9Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm9Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm9Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm9Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm9Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm9Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero EPwm9Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero // EPwm9Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm9Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm9Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm9Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm9Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm9Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm9Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm9Regs.CMPA.bit.CMPA = 0; EPwm9Regs.CMPB.bit.CMPB = 0; EPwm9Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm9Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm9Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm9Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm9Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm9Regs.DBRED = Inv_Deadtime_prd; // EPwm9Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm9Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm9Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm9Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm9Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm9Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm9Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm9Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm10(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm10Regs.TBPRD = Pwm_prd; // Set timer period EPwm10Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm10Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm10Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm10Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm10Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm10Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm10Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm10Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm10Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm10Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm10Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm10Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero EPwm10Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero // EPwm10Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm10Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm10Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm10Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm10Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm10Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm10Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm10Regs.CMPA.bit.CMPA = 0; EPwm10Regs.CMPB.bit.CMPB = 0; EPwm10Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm10Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm10Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm10Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm10Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm10Regs.DBRED = Inv_Deadtime_prd; // EPwm10Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm10Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm10Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm10Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm10Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm10Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm10Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm10Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm11(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm11Regs.TBPRD = Pwm_prd; // Set timer period EPwm11Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm11Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm11Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm11Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm11Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm11Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm11Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm11Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm11Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm11Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm11Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm11Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero EPwm11Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero // EPwm11Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm11Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm11Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm11Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm11Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm11Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm11Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm11Regs.CMPA.bit.CMPA = 0; EPwm11Regs.CMPB.bit.CMPB = 0; EPwm11Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm11Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm11Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm11Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm11Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // EPwm11Regs.DBRED = Inv_Deadtime_prd; // EPwm11Regs.DBFED = Inv_Deadtime_prd; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm11Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm11Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm11Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count���� 1 Up-Down�ϴ� 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm11Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); //EPwm11Regs.TBPHS.bit.TBPHS = PWMPrdCal(Pwm_Freq, Tbclk, CTRDIV) / 2; EPwm11Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm11Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } void InitEPwm12(float Pwm_Freq, float Pwm_Deadtime, unsigned int CTR_Mode, unsigned int Tbphs) { float Tbclk = 0; EALLOW; //EPwm12Regs.TBPRD = Pwm_prd; // Set timer period EPwm12Regs.TBPHS.bit.TBPHS = Tbphs; // Phase is 0 EPwm12Regs.TBCTR = 0x0000; // Clear counter // Setup Tbclk EPwm12Regs.TBCTL.bit.CTRMODE = CTR_Mode; // Count up EPwm12Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading //EPwm4Regs.TBCTL.bit.PHSDIR = TB_DOWN; EPwm12Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; EPwm12Regs.TBCTL.bit.PRDLD = TB_SHADOW; //EPwm12Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm12Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT EPwm12Regs.TBCTL.bit.CLKDIV = TB_DIV1; // Slow so we can observe on the scope EPwm12Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm12Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm12Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero EPwm12Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO_PRD; // load on CTR=Zero // EPwm12Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // EPwm12Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE; // EPwm12Regs.ETPS.bit.INTPRD = ET_1ST; // Set actions EPwm12Regs.AQCTLA.bit.CAU = AQ_CLEAR; // set actions for EPWM1A EPwm12Regs.AQCTLA.bit.CAD = AQ_SET; // EPwm12Regs.AQCTLB.bit.CBU = AQ_CLEAR; // set actions for EPWM1B // EPwm12Regs.AQCTLB.bit.CBD = AQ_SET; // Setup compare EPwm12Regs.CMPA.bit.CMPA = 0; EPwm12Regs.CMPB.bit.CMPB = 0; EPwm12Regs.TZCTL.bit.TZA = TZ_FORCE_LO; EPwm12Regs.TZCTL.bit.TZB = TZ_FORCE_LO; // Active high complementary PWMs - Setup the deadband EPwm12Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm12Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm12Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; //------------------TBPRD 및 Deadtime 자동계산 ---------------------// unsigned int HSPCLKDIV = 0, CLKDIV = 0, CTRMODE = 0, CTRDIV = 0; HSPCLKDIV = EPwm12Regs.TBCTL.bit.HSPCLKDIV; CLKDIV = EPwm12Regs.TBCTL.bit.CLKDIV; CTRMODE = EPwm12Regs.TBCTL.bit.CTRMODE; if (CTRMODE == 0 || CTRMODE == 1) CTRDIV = 1; // Up or Down count : 1, Up-Down : 2 else if (CTRMODE == 2) CTRDIV = 2; Tbclk = (SystemClock / ((HSPCLKDIV + 1) * (CLKDIV + 1))); //Tbclk = SYSCLKOUT / (HSPCLKDIV �� CLKDIV) EPwm12Regs.TBPRD = PwmPrdCal(Pwm_Freq, Tbclk, CTRDIV); EPwm12Regs.DBRED.bit.DBRED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EPwm12Regs.DBFED.bit.DBFED = PwmDeadtimeCal(Pwm_Deadtime, Tbclk); EDIS; } unsigned int PwmPrdCal(float PWM_FREQ, float Tbclk, unsigned int CTRDIV) { unsigned int Prd = 0; // Prd = (unsigned int) ((1/PWM_FREQ) * (Tbclk / CTRDIV ) + 1); Prd = (unsigned int) ((1 / PWM_FREQ) * (Tbclk / CTRDIV)); return Prd; } unsigned int PwmDeadtimeCal(float PWM_DEADTIME, float Tbclk) { unsigned Prd = 0; //Prd = (unsigned int) (PWM_DEADTIME * Tbclk + 1); Prd = (unsigned int) (PWM_DEADTIME * Tbclk); return Prd; } void InitEPwm1Gpio() { GPIO_setPadConfig(145, GPIO_PIN_TYPE_PULLUP); //EPMW1A GPIO_setPadConfig(146, GPIO_PIN_TYPE_PULLUP); //EPWM1B GPIO_setPinConfig(GPIO_145_EPWM1A); //EPMW1A GPIO_setPinConfig(GPIO_146_EPWM1B); //EPWM1B } void InitEPwm2Gpio() { GPIO_setPadConfig(147, GPIO_PIN_TYPE_PULLUP); //EPMW2A GPIO_setPadConfig(148, GPIO_PIN_TYPE_PULLUP); //EPWM2B GPIO_setPinConfig(GPIO_147_EPWM2A); //EPMW2A GPIO_setPinConfig(GPIO_148_EPWM2B); //EPWM2B } void InitEPwm3Gpio() { GPIO_setPadConfig(149, GPIO_PIN_TYPE_PULLUP); //EPMW3A GPIO_setPadConfig(150, GPIO_PIN_TYPE_PULLUP); //EPWM3B GPIO_setPinConfig(GPIO_149_EPWM3A); //EPMW3A GPIO_setPinConfig(GPIO_150_EPWM3B); //EPWM3B } void InitEPwm4Gpio() { GPIO_setPadConfig(151, GPIO_PIN_TYPE_PULLUP); //EPMW4A GPIO_setPadConfig(152, GPIO_PIN_TYPE_PULLUP); //EPWM4B GPIO_setPinConfig(GPIO_151_EPWM4A); //EPMW4A GPIO_setPinConfig(GPIO_152_EPWM4B); //EPWM4B } void InitEPwm5Gpio() { GPIO_setPadConfig(153, GPIO_PIN_TYPE_PULLUP); //EPMW5A GPIO_setPadConfig(154, GPIO_PIN_TYPE_PULLUP); //EPWM5B GPIO_setPinConfig(GPIO_153_EPWM5A); //EPMW5A GPIO_setPinConfig(GPIO_154_EPWM5B); //EPWM5B } void InitEPwm6Gpio() { GPIO_setPadConfig(155, GPIO_PIN_TYPE_PULLUP); //EPMW6A GPIO_setPadConfig(156, GPIO_PIN_TYPE_PULLUP); //EPWM6B GPIO_setPinConfig(GPIO_155_EPWM6A); //EPMW6A GPIO_setPinConfig(GPIO_156_EPWM6B); //EPWM6B } void InitEPwm7Gpio() { GPIO_setPadConfig(157, GPIO_PIN_TYPE_PULLUP); //EPMW7A GPIO_setPadConfig(158, GPIO_PIN_TYPE_PULLUP); //EPWM7B GPIO_setPinConfig(GPIO_157_EPWM7A); //EPMW7A GPIO_setPinConfig(GPIO_158_EPWM7B); //EPWM7B } void InitEPwm8Gpio() { GPIO_setPadConfig(159, GPIO_PIN_TYPE_PULLUP); //EPMW8A GPIO_setPadConfig(160, GPIO_PIN_TYPE_PULLUP); //EPWM8B GPIO_setPinConfig(GPIO_159_EPWM8A); //EPMW8A GPIO_setPinConfig(GPIO_160_EPWM8B); //EPWM8B } void InitEPwm9Gpio() { GPIO_setPadConfig(161, GPIO_PIN_TYPE_PULLUP); //EPMW9A GPIO_setPadConfig(162, GPIO_PIN_TYPE_PULLUP); //EPWM9B GPIO_setPinConfig(GPIO_161_EPWM9A); //EPMW9A GPIO_setPinConfig(GPIO_162_EPWM9B); //EPWM9B } void InitEPwm10Gpio() { GPIO_setPadConfig(163, GPIO_PIN_TYPE_PULLUP); //EPMW10A GPIO_setPadConfig(164, GPIO_PIN_TYPE_PULLUP); //EPWM10B GPIO_setPinConfig(GPIO_163_EPWM10A); //EPMW10A GPIO_setPinConfig(GPIO_164_EPWM10B); //EPWM10B } void InitEPwm11Gpio() { GPIO_setPadConfig(165, GPIO_PIN_TYPE_PULLUP); //EPMW11A GPIO_setPadConfig(166, GPIO_PIN_TYPE_PULLUP); //EPWM11B GPIO_setPinConfig(GPIO_165_EPWM11A); //EPMW11A GPIO_setPinConfig(GPIO_166_EPWM11B); //EPWM11B } void InitEPwm12Gpio() { GPIO_setPadConfig(167, GPIO_PIN_TYPE_PULLUP); //EPMW12A GPIO_setPadConfig(168, GPIO_PIN_TYPE_PULLUP); //EPWM12B GPIO_setPinConfig(GPIO_167_EPWM12A); //EPMW12A GPIO_setPinConfig(GPIO_168_EPWM12B); //EPWM12B }